Thanks so much!
This chip is causing me A LOT of troubles with the Linux kernel. I am on kernel 4.11, git bisecting back to previous versions, because it doesn't respect the PCI spec concerning the possibility to reprogram BAR.
pci 0008:00:04.0: BAR 5: pci_size=0, skipped -> cannot be programmed
pci 0008:00:04.0: ugly legacy mode stuff, skipped
I have already rewritten from scratch the support for u-boot-2019, pusthing the driver into a "memory mapped" model and, without touching the defailt setup of its BARs, it works (slowly but it works), while on Linux ... well, perhaps I'd better re implement it as "memory" mapped device rather than IO, this because forcing quirks on fixed memory addresses is simpler than forcing IO fixed address.
I'd really like to know if there is a better way, and the datasheet might tell it.
I will check it out tomorrow. Thank you again