Abandoned - Very frustrating RAM problem

[Nominal Animal]

Yup.  I always run a memtest over the weekend at least.  It's not a proof or guarantee of fitness, but if it finds failures, the mem is definitely no good in that configuration.

Many motherboards vary in their memory support depending on whether you fill only one pair or both.

On full-size desktop motherboards, it is common for the QVL to list fastest timings for only when one pair is used.
As an example, on an ASRock X670E Taichi Carrera with an AMD Ryzen 9 7900 (QVL), if you want to use all four sockets, you're limited to 5600 MHz (compared to 7600 MHz you can get when only two are used).

Thus, it is not at all strange to me that A+Y and B+X work well, while A+X and B+Y have memory errors, especially with age (tiny SMD chip caps losing capacitance as they age).

[radiolistener]

So let me get this straight... laptops or PCs that happen to have incompatible memory, work absolutely fine the first time? Honestly, that's blown my mind a bit but least that's something new I've learnt so thanks for that...

Yes, it depends on the case. In some cases, the memory error will happen every second. In others, it may take at least an hour or two to catch a single error. In the second case, the system may work fine for some time.

[nctnico]

Many motherboards vary in their memory support depending on whether you fill only one pair or both.

On full-size desktop motherboards, it is common for the QVL to list fastest timings for only when one pair is used.
As an example, on an ASRock X670E Taichi Carrera with an AMD Ryzen 9 7900 (QVL), if you want to use all four sockets, you're limited to 5600 MHz (compared to 7600 MHz you can get when only two are used).

This is a different issue. Using DIMM connectors it simply is no longer possible to create a design which supports these high speeds. This is why we'll be seeing more and more Camm   memory modules https://en.wikipedia.org/wiki/CAMM_(memory_module). At some point the laws of physics catch up.

Thus, it is not at all strange to me that A+Y and B+X work well, while A+X and B+Y have memory errors, especially with age (tiny SMD chip caps losing capacitance as they age).

Decoupling is primarily through ceramic capacitors and these don't really get bad due to age. Memory is compatible or not. Due to tolerances some combinations will perform better / worse but that means very little in the end.

[Bryn]

In case anybody didn't notice the modified thread title, the OP had ultimately decided to send the laptops back (I've seen his first post on this thread just there).

Don't know if we should continue discussing his problem in general or have the thread locked, whatever's suitable.

[Nominal Animal]

This is a different issue.

No.  There is a reason why most motherboards support high clock frequencies on one full DIMM channel, but much lower frequencies when both DIMM channels are in use, and it isn't "physics" per se.  After all, it is the exact same connectors and physical devices.

You can clearly see in the QVL I linked to that many are only qualified to be used to fill one channel (one pair); and very few are qualified to fill both channels (two pairs, four DIMM sticks).

(You can argue that of course the base reason comes down to physics, because everything physical comes down to physics, really.  Here, the two channels are not independent, but driven by the same memory controller, so the two channels do interact at least electrically.  If this is what you call "a different issue", and the physical limitation when using 4 DIMMs instead of just 2, then I'd agree somewhat: to me, it is more like a design limitation in the memory controllers.  As the motherboard ages, the memory controller becomes slightly more limited wrt. clock and signal pulse shapes and whatnot that work without errors; MLCC aging is an important part of that.)

Decoupling is primarily through ceramic capacitors and these don't really get bad due to age.

They age enough to excarberate the differences between individual DIMM sticks.  For example, for X5R, it is about 6% after the first 1000 hours of use. 

Note that I'm specifically referring to the caps on the motherboard, not the ones on the memory sticks.  For details on MLCC aging, do check out the Würth Electronic Support Note on MLCC aging, for example.  Also note that four years of almost daily use, 8h per day, corresponds to about 10000h of use, so those scales are very relevant here.

If this happened with a brand new motherboard and memory, I'd be very suspicious.  When it happens with a motherboard that is five to ten years old, I expect this kind of quirks due to aging, and just deal with it; I've built and maintained enough Intel/AMD PCs to have seen this in practice for myself.

[Someone]

This is a different issue.

No.  There is a reason why most motherboards support high clock frequencies on one full DIMM channel, but much lower frequencies when both DIMM channels are in use, and it isn't "physics" per se.  After all, it is the exact same connectors and physical devices.

You can clearly see in the QVL I linked to that many are only qualified to be used to fill one channel (one pair); and very few are qualified to fill both channels (two pairs, four DIMM sticks).

(You can argue that of course the base reason comes down to physics, because everything physical comes down to physics, really.  Here, the two channels are not independent, but driven by the same memory controller, so the two channels do interact at least electrically.  If this is what you call "a different issue", and the physical limitation when using 4 DIMMs instead of just 2, then I'd agree somewhat: to me, it is more like a design limitation in the memory controllers.  As the motherboard ages, the memory controller becomes slightly more limited wrt. clock and signal pulse shapes and whatnot that work without errors; MLCC aging is an important part of that.)

Decoupling is primarily through ceramic capacitors and these don't really get bad due to age.

They age enough to excarberate the differences between individual DIMM sticks.  For example, for X5R, it is about 6% after the first 1000 hours of use. 

Note that I'm specifically referring to the caps on the motherboard, not the ones on the memory sticks.  For details on MLCC aging, do check out the Würth Electronic Support Note on MLCC aging, for example.  Also note that four years of almost daily use, 8h per day, corresponds to about 10000h of use, so those scales are very relevant here.

If this happened with a brand new motherboard and memory, I'd be very suspicious.  When it happens with a motherboard that is five to ten years old, I expect this kind of quirks due to aging, and just deal with it; I've built and maintained enough Intel/AMD PCs to have seen this in practice for myself.

The next woo-woo computer fix (thinking here of freezing HDD with seized bearings, or the half arsed attempts at reflowing GPUs) will be annealing ceramic caps ? bake your ram sticks at 170 degrees for 2 hours?

[Nominal Animal]

"Bake until you see the plastic and epoxy parts start to change color.  They're actually designed to do so, but the Industry Cabal has kept it secret to increase computer sales and reduce repairs."

[nctnico]

This is a different issue.

No.  There is a reason why most motherboards support high clock frequencies on one full DIMM channel, but much lower frequencies when both DIMM channels are in use, and it isn't "physics" per se.  After all, it is the exact same connectors and physical devices.

It is a physics limit: electrical loading of the signal lines which degrades signal integrity to a point where it is no longer reliable when two memory modules are connected in parallel. You have to keep in mind that memory with a 5600 speed grade needs a 5.6GHz+ bandwidth on the signals. It is a miracle a -from an RF point of view- ultra crappy connector like a DIMM slot can be pushed to supports these kind of frequencies. The problem really is in the connector system used for traditional memory slots like DIMM. A CAMM module does not have this limitation as the memory can be connected in parallel on the module itself while retaining excellent signal integrity.

[Nominal Animal]

It is a physics limit: electrical loading of the signal lines which degrades signal integrity to a point where it is no longer reliable when two memory modules are connected in parallel. You have to keep in mind that memory with a 5600 speed grade needs a 5.6GHz+ bandwidth on the signals. It is a miracle a -from an RF point of view- ultra crappy connector like a DIMM slot can be pushed to supports these kind of frequencies.

You forget: the example MB and processor supports 7600 MHz when using one full channel, two DIMM modules in the exact same connector.

It has been extremely typical for the maximum DIMM clock for four modules to be a quarter less than for two modules.  Much less when using ECC memory, of course.  This was just an example of the "quirks" in current Intel/AMD memory controllers, though.

Consider the phase space –– multidimensional region or regions where each axis is one of the properties like clock frequency, voltage, current, bus capacitive loading, and so on –– of each individual DIMM module.  Each has their own error-free region, and that region tends to shrink as the related components (here, those on the motherboard) age, even if just by a few percentage points.  Even if we ignore the interactions between the memory channels, it is the intersection of all DIMM modules' error-free region we need to operate in.  It is is obvious that as we increase the number of modules, the intersection region shrinks, and that individual differences in DIMMs can make the difference between reliable and unreliable configurations even when using ostensibly identical modules.