8-bit uC - is there even a point?

[brucehoult]

I guess that after 14 paged the conclusion is that there is a point to 8 bit microcontrollers.

For sufficiently low-performance applications (of which there are untold number), what reasonable person could say otherwise?

I do note however that I never saw what I would call a true 8 bit processor -- they are all 8/16 hybrid designs with 8 bit ALUs and some 8 bit and some 16 bit registers.

In any *other* bitness for CPUs -- 16, 32, 64, 128 -- the reference number is the size of the directly-accessible address space and therefore of any registers that hold addresses, including the Program Counter.

The traditional 1970s "8 bit" processors *all* had at least some 16 bit registers internally and almost all brought out a full 16 bit address bus on their packages e.g. 2650, 8080, z80, 6800, 6502, 8051. The SC/MP only brought out a 12 bit address bus but it had a 16 bit PC and three 16 bit pointer registers and A12-A15 were multiplexed onto the data bus. The RCA 1802 had 16 registers of 16 bits each and a 16 bit address space, and it multiplexed the 16 bit addresses onto two phases of an 8 bit address bus.

Even 4 bit processors have at least 10 bits of program counter. The key thing is the software can only count to 15.

As long as you've got either AND or OR plus NOT (possibly combined e.g. NAND), or the ability to test and branch based on a bit, even a 1-bit ALU lets software count to or add/sub/mul/div as large numbers as there are bits of memory to store.

Slowly.

But you still need a decent address space, especially for the program.

[NorthGuy]

I do note however that I never saw what I would call a true 8 bit processor -- they are all 8/16 hybrid designs with 8 bit ALUs and some 8 bit and some 16 bit registers.

PIC10F320

[Mr. Scram]

For sufficiently low-performance applications (of which there are untold number), what reasonable person could say otherwise?

I do note however that I never saw what I would call a true 8 bit processor -- they are all 8/16 hybrid designs with 8 bit ALUs and some 8 bit and some 16 bit registers.

In any *other* bitness for CPUs -- 16, 32, 64, 128 -- the reference number is the size of the directly-accessible address space and therefore of any registers that hold addresses, including the Program Counter.

The traditional 1970s "8 bit" processors *all* had at least some 16 bit registers internally and almost all brought out a full 16 bit address bus on their packages e.g. 2650, 8080, z80, 6800, 6502, 8051. The SC/MP only brought out a 12 bit address bus but it had a 16 bit PC and three 16 bit pointer registers and A12-A15 were multiplexed onto the data bus. The RCA 1802 had 16 registers of 16 bits each and a 16 bit address space, and it multiplexed the 16 bit addresses onto two phases of an 8 bit address bus.

Are we going for the "No true Schotsman" now?

[brucehoult]

I do note however that I never saw what I would call a true 8 bit processor -- they are all 8/16 hybrid designs with 8 bit ALUs and some 8 bit and some 16 bit registers.

PIC10F320

11 bit program address space, and the PC itself is 9 bits within a page. That's architecture. True, that particular chip only has 256 words of program space implemented, but you could always do that with an 8080 or 6502 too, if you wanted (and it was common to do so with the 1802).

Going back further, the PDP8 of course had a 12 bit address space and crude banking to extend it, very similar to PIC.

[NorthGuy]

I do note however that I never saw what I would call a true 8 bit processor -- they are all 8/16 hybrid designs with 8 bit ALUs and some 8 bit and some 16 bit registers.

PIC10F320

11 bit program address space, and the PC itself is 9 bits within a page. That's architecture. True, that particular chip only has 256 words of program space implemented, but you could always do that with an 8080 or 6502 too, if you wanted (and it was common to do so with the 1802).

Going back further, the PDP8 of course had a 12 bit address space and crude banking to extend it, very similar to PIC.

You mean ISA address bus? I wouldn't single out 8-bitters. The mismatch is rather common:

16-bit 8086 had 20-bit address bus, PIC24 has 23-bit address bus.

Or the other way around:

32-bit MIPS has 29-bit address bus, 64-bit ARM has 48-bit address bus, x64 has 48-bit address bus.

[brucehoult]

I do note however that I never saw what I would call a true 8 bit processor -- they are all 8/16 hybrid designs with 8 bit ALUs and some 8 bit and some 16 bit registers.

PIC10F320

11 bit program address space, and the PC itself is 9 bits within a page. That's architecture. True, that particular chip only has 256 words of program space implemented, but you could always do that with an 8080 or 6502 too, if you wanted (and it was common to do so with the 1802).

Going back further, the PDP8 of course had a 12 bit address space and crude banking to extend it, very similar to PIC.

You mean ISA address bus? I wouldn't single out 8-bitters. The mismatch is rather common:

16-bit 8086 had 20-bit address bus, PIC24 has 23-bit address bus.

Or the other way around:

32-bit MIPS has 29-bit address bus, 64-bit ARM has 48-bit address bus, x64 has 48-bit address bus.

No, not address bus. That's irrelevant and changes frequently between software compatible processors. It's the size of the registers that counts, in particular the PC and registers used as data pointers.

[westfw]

Usually architectures are ranked by the apparent size of their ALU.  ("apparent", because it seems like the Z80 had a 4bit ALU, and just always did at least two operations...)
I'd rate the 8bit PICs (PIC16f...) as true 8bit architectures.  8bit ALU, 8bit register(s), less than 8bit address space for data (until you add the banking.)  The PC and instruction word are wider, but "Harvard architecture", so those are pretty separate from everything else.  (and the baseline PICs with essentually 9bit PCs (plus another bank) and only 8 bits of address in a "call" instruction!)

5V designs

not been mentioned yet: Toshiba has some pretty substantial CM3 ARM chips that will run on 5V.
The NXP ones are the "Kinetis E" series.So they're not uncommon.  I think the surprising bit is that none of the "hobbyist" vendors (Arduino, Adafruit, Sparkfun, PJRC, etc) seems to have jumped on any of the 5V 32bit cpus...

[JPortici]

i bet that's because you can't get them for peanuts in china

[technix]

Usually architectures are ranked by the apparent size of their ALU.  ("apparent", because it seems like the Z80 had a 4bit ALU, and just always did at least two operations...)
I'd rate the 8bit PICs (PIC16f...) as true 8bit architectures.  8bit ALU, 8bit register(s), less than 8bit address space for data (until you add the banking.)  The PC and instruction word are wider, but "Harvard architecture", so those are pretty separate from everything else.  (and the baseline PICs with essentually 9bit PCs (plus another bank) and only 8 bits of address in a "call" instruction!)

How would you call a configurable soft processor that has 16-bit registers and program counter but selectable 8-bit or 16-bit ALU? (SBT-16 core)

How would you call a processor with aligned 64-bit registers and program counter, fixed 32-bit instruction length, registers that are addressable down to byte level, and an ALU that has control signals allowing it to be broken into shorter units for SIMD? (for example add.q b1,b2,b3 treats data in registers q2 and q3 each as 8 individual bytes, and put the 8 separate sums into q1.)

5V designs

not been mentioned yet: Toshiba has some pretty substantial CM3 ARM chips that will run on 5V.
The NXP ones are the "Kinetis E" series.So they're not uncommon.  I think the surprising bit is that none of the "hobbyist" vendors (Arduino, Adafruit, Sparkfun, PJRC, etc) seems to have jumped on any of the 5V 32bit cpus...

[coppice]

I guess that after 14 paged the conclusion is that there is a point to 8 bit microcontrollers.

For sufficiently low-performance applications (of which there are untold number), what reasonable person could say otherwise?

I do note however that I never saw what I would call a true 8 bit processor -- they are all 8/16 hybrid designs with 8 bit ALUs and some 8 bit and some 16 bit registers.

In any *other* bitness for CPUs -- 16, 32, 64, 128 -- the reference number is the size of the directly-accessible address space and therefore of any registers that hold addresses, including the Program Counter.

The traditional 1970s "8 bit" processors *all* had at least some 16 bit registers internally and almost all brought out a full 16 bit address bus on their packages e.g. 2650, 8080, z80, 6800, 6502, 8051. The SC/MP only brought out a 12 bit address bus but it had a 16 bit PC and three 16 bit pointer registers and A12-A15 were multiplexed onto the data bus. The RCA 1802 had 16 registers of 16 bits each and a 16 bit address space, and it multiplexed the 16 bit addresses onto two phases of an 8 bit address bus.

Even 4 bit processors have at least 10 bits of program counter. The key thing is the software can only count to 15.

As long as you've got either AND or OR plus NOT (possibly combined e.g. NAND), or the ability to test and branch based on a bit, even a 1-bit ALU lets software count to or add/sub/mul/div as large numbers as there are bits of memory to store.

Slowly.

But you still need a decent address space, especially for the program.

4 bit MCUs were an excellent choice for many early MCU applications, because so many applications wanted them to behave as decimal machines (e.g. in calculators). They only really needed to count up to nine. If you've ever had access to much source code for applications on the TMS1000 (the first successful MCU), its surprising how often applications like shower heaters, and toaster controllers, where there was no decimal UI, made the chip mimic a BCD machine.

Single bit cores were an excellent choice for high throughput machines, like the MPP, when you could distribute a single program to a huge number of 1 bit cores. As propagation delays began to dominate over switching times, that no longer really worked.

[Fungus]

Usually architectures are ranked by the apparent size of their ALU.  ("apparent", because it seems like the Z80 had a 4bit ALU, and just always did at least two operations...)
I'd rate the 8bit PICs (PIC16f...) as true 8bit architectures.  8bit ALU, 8bit register(s), less than 8bit address space for data (until you add the banking.)  The PC and instruction word are wider, but "Harvard architecture", so those are pretty separate from everything else.  (and the baseline PICs with essentually 9bit PCs (plus another bank) and only 8 bits of address in a "call" instruction!)

How would you call a configurable soft processor that has 16-bit registers and program counter but selectable 8-bit or 16-bit ALU? (SBT-16 core)

If it has 16-bit registers and a 16-bit ADD instruction then it's 16 bit.

[NorthGuy]

I do note however that I never saw what I would call a true 8 bit processor -- they are all 8/16 hybrid designs with 8 bit ALUs and some 8 bit and some 16 bit registers.

PIC10F320

11 bit program address space, and the PC itself is 9 bits within a page. That's architecture. True, that particular chip only has 256 words of program space implemented, but you could always do that with an 8080 or 6502 too, if you wanted (and it was common to do so with the 1802).

Going back further, the PDP8 of course had a 12 bit address space and crude banking to extend it, very similar to PIC.

You mean ISA address bus? I wouldn't single out 8-bitters. The mismatch is rather common:

16-bit 8086 had 20-bit address bus, PIC24 has 23-bit address bus.

Or the other way around:

32-bit MIPS has 29-bit address bus, 64-bit ARM has 48-bit address bus, x64 has 48-bit address bus.

No, not address bus. That's irrelevant and changes frequently between software compatible processors. It's the size of the registers that counts, in particular the PC and registers used as data pointers.

PIC10F320 has 8-bit PC (PCL register @0x02) and 8-bit data pointer (FSR register @0x04).

The only way where there might be some extra space is the code for GOTO instruction, which has room for 11 bits, bit only 8 bits are used.

[brucehoult]

Usually architectures are ranked by the apparent size of their ALU.  ("apparent", because it seems like the Z80 had a 4bit ALU, and just always did at least two operations...)
I'd rate the 8bit PICs (PIC16f...) as true 8bit architectures.  8bit ALU, 8bit register(s), less than 8bit address space for data (until you add the banking.)  The PC and instruction word are wider, but "Harvard architecture", so those are pretty separate from everything else.  (and the baseline PICs with essentually 9bit PCs (plus another bank) and only 8 bits of address in a "call" instruction!)

How would you call a configurable soft processor that has 16-bit registers and program counter but selectable 8-bit or 16-bit ALU? (SBT-16 core)

If it has 16-bit registers and a 16-bit ADD instruction then it's 16 bit.

z80 has some 16 bit registers and 16 bit add instructions.  Specifically, you can add any of BC/DE/SP to any of HL/IX/IY, or add HL/IX/IY to themselves.

And yet the z80 is commonly referred to as an 8 bit processor. Which is my original point: the so-called 8 bit processors were all 8/16 bit hybrids. (except the very smallest PICs. I'll give them that)

[Fungus]

z80 has some 16 bit registers and 16 bit add instructions.  Specifically, you can add any of BC/DE/SP to any of HL/IX/IY, or add HL/IX/IY to themselves. And yet the z80 is commonly referred to as an 8 bit processor.

What you're describing is what we call "CISC" - the Z80 was a "Complex Instruction Set" design, not a "hybrid".

The clue is in the fact that "ADD A,L" takes 4 clock cycles but "ADD HL,DE" takes 15.

Internally it's all 8 bits but it can perform a sequence of operations for a single instruction.

The Z80 even has instructions that enter an internal loop and repeat a sequence a specified number of times while counting down a register, that's pure CISC.

(and, yes, you can unroll those loops for speed...  )

Bottom line: The Z80 is 8-bit.

the so-called 8 bit processors were all 8/16 bit hybrids. (except the very smallest PICs. I'll give them that)

There was nothing 16-bit about (eg.) a MOS 6502.

[brucehoult]

z80 has some 16 bit registers and 16 bit add instructions.  Specifically, you can add any of BC/DE/SP to any of HL/IX/IY, or add HL/IX/IY to themselves. And yet the z80 is commonly referred to as an 8 bit processor.

What you're describing is what we call "CISC" - the Z80 was a "Complex Instruction Set" design, not a "hybrid".

The clue is in the fact that "ADD A,L" takes 4 clock cycles but "ADD HL,DE" takes 15.

Internally it's all 8 bits but it can perform a sequence of operations for a single instruction.

That's one particular implementation. You could build a new implementation of the z80 instruction set today that did both 8 bit and 16 bit operations in 1 clock cycle.

The common z80 chip is an implementation of an 8/16 bit instruction set that internally uses an 8 bit ALU. (Someone in this thread said it actually uses a 4 bit ALU! Maybe .. I really don't know.)

the so-called 8 bit processors were all 8/16 bit hybrids. (except the very smallest PICs. I'll give them that)

There was nothing 16-bit about (eg.) a MOS 6502.

Addresses are 16 bits. The PC is 16 bits. You can store 16 bit pointers in two consecutive memory locations in zero page and with a single LDA (zp),Y instruction fetch them into an internal unnamed 16 bit register, add the Y register to that register (*with* carry between pages), and use that register as the address of a byte to load (or store, or add etc).

[Fungus]

Internally it's all 8 bits but it can perform a sequence of operations for a single instruction.

That's one particular implementation. You could build a new implementation of the z80 instruction set today that did both 8 bit and 16 bit operations in 1 clock cycle.

It's the implementation that we all used, and the chips that we did it with were 8-bit chips.

There was nothing 16-bit about (eg.) a MOS 6502.

Addresses are 16 bits. The PC is 16 bits. You can store 16 bit pointers in two consecutive memory locations in zero page and with a single LDA (zp),Y instruction fetch them into an internal unnamed 16 bit register, add the Y register to that register (*with* carry between pages), and use that register as the address of a byte to load (or store, or add etc).

16-bit PC doesn't mean 16 bit processing. The "LDA (zp),Y" instruction is a bit of CISC.

nb. Nobody used "LDA (zp),Y" because it was too slow, we preferred self-modifying code instead (modify an "LDA absolute,Y" instruction).

[brucehoult]

nb. Nobody used "LDA (zp),Y" because it was too slow, we preferred self-modifying code instead (modify an "LDA absolute,Y" instruction).

Woz used the (zp),Y addressing mode five times in SWEET16, widely acknowledged as some of the best 300 bytes of 6502 code (not to mention one of the best bytecode interpreters) you'll find anywhere.

http://www.6502.org/source/interpreters/sweet16.htm#The_Story_of_Sweet_Sixteen

Self-modifying code was useful for memcpy() or something like that. Not for normal programs.

[technix]

Usually architectures are ranked by the apparent size of their ALU.  ("apparent", because it seems like the Z80 had a 4bit ALU, and just always did at least two operations...)
I'd rate the 8bit PICs (PIC16f...) as true 8bit architectures.  8bit ALU, 8bit register(s), less than 8bit address space for data (until you add the banking.)  The PC and instruction word are wider, but "Harvard architecture", so those are pretty separate from everything else.  (and the baseline PICs with essentually 9bit PCs (plus another bank) and only 8 bits of address in a "call" instruction!)

How would you call a configurable soft processor that has 16-bit registers and program counter but selectable 8-bit or 16-bit ALU? (SBT-16 core)

If it has 16-bit registers and a 16-bit ADD instruction then it's 16 bit.

SBT-16 has 16-bit registers which are byte addressable for narrower instructions, and its ALU instruction can do 16-bit single, 8-bit single or 8-bit x2 SIMD. Is it 8-bit or is it 16-bit?

SBT-64 has 64-bit registers which are aligned 4-byte, 2-byte or byte addressable for narrower instructions , and its ALU instructions can do 64-bit single, 32-bit single, 16-bit single, 8-bit single, 32bit x2 SIMD, 16-bit x2 SIMD, 16-bit x4 SIMD, 8-bit x2 SIMD, 8-bit x4 SIMD or 8-bit x8 SIMD. Is it 8-bit 16-bit, 32-bit or 64-bit?

[Fungus]

Woz used the (zp),Y addressing mode five times in SWEET16, widely acknowledged as some of the best 300 bytes of 6502 code (not to mention one of the best bytecode interpreters) you'll find anywhere.

Argument from authority? 

a) It fits the job really well in that instance, and
b) It was in ROM - no self-modifying code possible! 
c) Note that it's a "solution to the problem of handling 16 bit data, notably pointers, with an 8 bit microprocessor" )

PS: I met Woz a couple of years back. 

[Fungus]

SBT-16 has 16-bit registers which are byte addressable for narrower instructions, and its ALU instruction can do 16-bit single, 8-bit single or 8-bit x2 SIMD. Is it 8-bit or is it 16-bit?

Figure it out by yourself! There's enough information in this thread for you to do so. 

[brucehoult]

Woz used the (zp),Y addressing mode five times in SWEET16, widely acknowledged as some of the best 300 bytes of 6502 code (not to mention one of the best bytecode interpreters) you'll find anywhere.

Argument from authority? 

a) It fits the job really well in that instance, and
b) It was in ROM - no self-modifying code possible! 
c) Note that it's a "solution to the problem of handling 16 bit data, notably pointers, with an 8 bit microprocessor" )

PS: I met Woz a couple of years back. 

Pretty sure Woz was capable of copying a small loop into RAM in ZP or page 3 if he wanted to.

This whole thread started with the observation that by modern definitions as N-bit ISA is one which has N-bit pointers and the only exception to this is that the so-called 8 bit processors actually had 16 bit pointers.

I have a card (ticket for a breakfast at which they were the star guests) Woz and Hertzfeld signed for me in Wellington NZ in 1986.

[technix]

SBT-16 has 16-bit registers which are byte addressable for narrower instructions, and its ALU instruction can do 16-bit single, 8-bit single or 8-bit x2 SIMD. Is it 8-bit or is it 16-bit?

Figure it out by yourself! There's enough information in this thread for you to do so. 

To my eyes SBT-16 is a genuine 16-bit processor, and SBT-64 is a genuine 64-bit processor. What I feel here is that people is getting program counter length, data register length and ALU length confused, so I threw those SIMD-heavy processors to get some clarifications.

[legacy]

=
confused

oh, well, confusion is the white noise background I have got with every MIPS64 support packages I have worked on, where I have always had to understand *what* they meant with "pointer" since sometimes they were defined 64bit in the doc of the BSP, but sometimes 32bit in the definition files, a complete mess 

[Fungus]

This whole thread started with the observation that by modern definitions as N-bit ISA is one which has N-bit pointers and the only exception to this is that the so-called 8 bit processors actually had 16 bit pointers.

That wouldn't be my definition at all. To me it's about the ALU and data processing, not the width of the address bus.

Having less wires going into the ALU directly affects processing power and speed of execution, having more or less address lines makes no difference at all.

the only exception to this is that the so-called 8 bit processors actually had 16 bit pointers.

Not true. The 8086/80286 had 16-bit registers, 16-bit ALU and 20-bit pointers (22-bit pointers on the 80286 IIRC).

Plus: Many, many 32 and 64 bit processors don't have the same number of address lines as bits in the address registers. eg. Are the Motorola 68000 and Intel 80386 24-bit processors? I don't think you'll find many people arguing that case.

[Fungus]

There's another argument that it should be the size of the data bus but there's quite a few chips that had a half-size data bus to make the system cheaper to build.

eg. Intel 8088, Motorola 68008.

Those chips need to do two separate reads for every 16-bit memory access that the "full-width" versions do.

Both those chips are classed as 16-bit so that's not it, either.