EEVblog #683 - Rigol DS1000Z & DS2000 Oscilloscope Jitter Problems

[i4004]

These inputs are being generated by an ADF4360-7 frequency synthesizer, which has as its base clock a 25MHz crystal/resonator/oscillator block (not sure exactly, marked "CETDCJ 25.000").

given that some users don't have the problem, would it be possible some units have different 25mhz (ie botched) crystals that "ring" in a peculiar way and thereby influence the synthesizer?

[David Hess]

So, it seems the sample clock *is* spread.  Maybe not on purpose?   It's difficult to unwind if you're trying to get a decent FFT out of the thing.

The limited resolution of the DSO's built in FFT function may not be able to see it.

Below are a couple shots from an SA looking at the ADC (HMCAD1511) CLKP and CLKN inputs with a differential probe.  These inputs are being generated by an ADF4360-7 frequency synthesizer, which has as its base clock a 25MHz crystal/resonator/oscillator block (not sure exactly, marked "CETDCJ 25.000").

I'm noting that the synthesizer output has discrete jumps of 100kHz.  Now where have we seen that number before??

As Adam Savage would say, "Well, there's your problem."

I do not see any configuration in the ADF4360-7 frequency synthesizer for generating a spread spectrum output.  Maybe the modulation is from the 25 MHz clock source.

[(In)Sanity]

I had posted a while back that my DS2000A series was showing significantly less jitter between 14.7x Mhz and 14.9x Mhz.   I forget the exact numbers and I'm too lazy to go look at my post     I found it odd that it had a sweet spot. 

In any event might be something to look at mathematically. 

Jeff

[MarkL]

Below are a couple shots from an SA looking at the ADC (HMCAD1511) CLKP and CLKN inputs with a differential probe.  These inputs are being generated by an ADF4360-7 frequency synthesizer, which has as its base clock a 25MHz crystal/resonator/oscillator block (not sure exactly, marked "CETDCJ 25.000").

I'm noting that the synthesizer output has discrete jumps of 100kHz.  Now where have we seen that number before??

As Adam Savage would say, "Well, there's your problem."

I do not see any configuration in the ADF4360-7 frequency synthesizer for generating a spread spectrum output.  Maybe the modulation is from the 25 MHz clock source.

The 25MHz input is very pure.

I notice, however, the loop filter is external between CP and VTUNE (VTUNE is the VCO input).  There's a 100kHz tone on the VTUNE pin, but's hard to say what the origin could be.  Perhaps their filter design has a problem and it introduces some instability.

Given that people are seeing varying amounts of jitter at 5us, it seems unlikely it's intended (such as to reduce EMI as has been suggested).  Rather the difference is from varying amounts of ingress noise or loop instability from component differences.

[David Hess]

I get all that,  I just wonder what additional low freq is getting adding in to the trigger circuit perhaps internally.   My 2465B doesn't have any issues with jitter on the same exact signal with the same cable, same impedance..etc..etc.  So I have to presume the 2000A I have is getting some other noise in the trigger circuit at some point.   I also notice the problem doesn't seam to exist on the External trigger,  at least on mine.  Then again I can't get it to AC trigger with the external connection without a cap inline.

Since the 1000Z and 2000A triggers are done digitally in the FPGA, I assume the AC trigger coupling code is just broken.

It is not entirely clear how the external trigger input works on the 2000A.  I assume it operates as an analog trigger with some simple signal conditioning and a comparator driving one of the FPGA digital inputs.  AC coupling, low frequency, and high frequency reject would need to be implemented with analog circuits then so if they left those out, then they are not going to be adding them with a firmware update.

Actually they must be doing something a little more sophisticated to get better timing resolution that the FPGA processing clock will provide.

[Bud]

The 25MHz input is very pure.

What a horrible clock for an ADC.  The PLL is unlocked. Nowhere in the datasheet it says spread spectrum. Can you check the 4360's Lock pin?

[Bud]

I'm not saying the user interface can't be improved

Deleting measurements please... Please change UI to delete measurements by the same left gray buttons they are activated.
 

[MarkL]

The 25MHz input is very pure.

What a horrible clock for an ADC.  The PLL is unlocked. Nowhere in the datasheet it says spread spectrum. Can you check the 4360's Lock pin?

That's the first thing I looked for.  There is no dedicated lock pin.  The MUXOUT pin can be selected to be Analog Lock, Digital Lock, Scaled RF, Scaled Ref, or a few other things.  Without going to the next level and decoding the SPI bus, I don't know what's selected on MUXOUT.  All I can say that is that it's a constant high and that unfortunately doesn't say anything.

[Bud]

Yes it is multiplexed, I forget. Here is a proper output from a 4360-8. The 6.5 MHz spurs are the phase  frequency detector artifacts from a 19.44MHz reference clock.

EDIT: And I remember I got something looking like the pics you posted when my PLL was not locked, that is why it ringed me a bell. I believe (I forget details) it was a overdrive problem on the reference input, the p-p voltage from a single-ended CMOS oscillator was too high, I had to squeeze in a 2-resistor voltage divider on 4360's Ref Clk input. Try checking Ref clock amplitude against the PLL datasheet.

[MarkL]

That looks like a nice output.

So we don't have a lock pin, but we can look at the Charge Pump pin.  Below is what it's doing.  I would expect it to be more symmetric if it was locked.

If you have one there (and that wasn't an old picture), what does your CP pin look like?

[MarkL]

EDIT: And I remember I got something looking like the pics you posted when my PLL was not locked, that is why it ringed me a bell. I believe (I forget details) it was a overdrive problem on the reference input, the p-p voltage from a single-ended CMOS oscillator was too high, I had to squeeze in a 2-resistor voltage divider on 4360's Ref Clk input. Try checking Ref clock amplitude against the PLL datasheet.

Ref clock has almost a full 3.3V swing.  It's AC coupled into the 4360, -0.3 to +3.0 on the Ref pin.  Avdd is 3.3V.  That would be ok if I'm reading the spec right.

Were you driving it beyond the rails that caused the problem?

[David Hess]

Below are a couple shots from an SA looking at the ADC (HMCAD1511) CLKP and CLKN inputs with a differential probe.  These inputs are being generated by an ADF4360-7 frequency synthesizer, which has as its base clock a 25MHz crystal/resonator/oscillator block (not sure exactly, marked "CETDCJ 25.000").

I'm noting that the synthesizer output has discrete jumps of 100kHz.  Now where have we seen that number before??

As Adam Savage would say, "Well, there's your problem."

I do not see any configuration in the ADF4360-7 frequency synthesizer for generating a spread spectrum output.  Maybe the modulation is from the 25 MHz clock source.

The 25MHz input is very pure.

I notice, however, the loop filter is external between CP and VTUNE (VTUNE is the VCO input).  There's a 100kHz tone on the VTUNE pin, but's hard to say what the origin could be.  Perhaps their filter design has a problem and it introduces some instability.

Given that people are seeing varying amounts of jitter at 5us, it seems unlikely it's intended (such as to reduce EMI as has been suggested).  Rather the difference is from varying amounts of ingress noise or loop instability from component differences.

I forgot to mention that a 100 kHz FM modulation source would appear as sidebands at increments of 100 kHz.

I doubt spread spectrum modulation was intended and suggested that it might have been included accidentally through a purchasing mistake.  Some DSOs in the past used frequency modulation of the sample clock to prevent synchronous sampling but when they did this, they also compensated for it after sampling so it was transparent to the user.

That the problem is originating in the PLL clock multiplier makes sense if the reference is divided down to 100 kHz first by the R divider which is certainly possible.  Maybe the wrong parts got used in the loop filter.

[jlmoon]

I have a 2202, and experience the jitter across the entire horizontal position.  AC triggering, it  does not matter what position in relation to 0 center point ,  I have also noticed if you step up the memory depth to the higher levels the scope exhibits  some pretty interesting changes to the almost synced jitter.  I can also vary the input and make the jitter synchronize  with my input to make the waveform almost sync or stand still.


my 2c worth

[Nonorthogonal]

This scope has some rock solid jitter. This is with no AC coupling... perhaps Rigol will accept an RMA??

You can make your own sad charts with the attached Python script... 

[Bud]

If you have one there (and that wasn't an old picture), what does your CP pin look like?

I do not have the board handy, I need  to look for it. But if to do some math, on my screenshot the PFD spurs are at roughly 62dBc, and the carrier is at 0dBm, that is power, converting to voltage is 0.5mV p-p spurs on the PLL output. I am not sure how much leakage from PFD to RF Out is specified for the part but would probably not be anywhere close to the ones on the screenshots you captured.

Looking at your screenshots it is hard to estimate power in a 100kHz bin , but lets say judging by the envelope about -30dBm   which is after conversion to voltage is 20mV p-p. You measured 50mV p-p but as I said it was a rough estimate and the loop filter leakage may be attenuating the ripple on the loop filter pins.

I am falling sick at the moment, hope my calc made sense.

we can post a question on AD forum if your waveform makes sense to them , their engineers are pretty responsive.

[Bud]

That looks like a nice output.

ADF4360 would not the best PLL, I did not like the spurs, that is why the proto board was shelved.
Look at what one can get from the Linear's LTC6946

Be-e-e-a-a-u-u-ty
 

Note the center frequency. This is what I call a home brewed clock oscillator ...
And by the way it was referenced from a 10MHz Ovenized CXO. Rock solid, man. I had to use a prescaler to get the frequency down to measure on my trusty HP counter referenced from my Rubidium standard.
Oh man, sex on a stick
 

[poida_pie]

the DS1054Z arrived today.

One more data point:
Software version: 00.04.02.SP3
Board version: 0.1.1

Got teh jitters.
But also got >100MHz bandwidth too after applying some codes.


What a sensational DSO for the up and coming EE kids who are playing with Arduino/R-Pi/Pics/etc/etc
and inventing a new world as fast as they can!

And what is your sinewave  quality (specifications)  in picture 1 and 2.
Do you know how much it have jitter measured over 5us time period.

here is the DS1054Z of mine with the same 20Mhz sin from the fun gen at different delays.
0,5,20,25,30,100 us.
At 5 and 25 us delay, the jitter is clear to see. Nice signal out to 100us.

Test conditions:
Rigol DG1022 fun gen, via decent coax cable, 50 ohm terminated into ch1 of DS1054Z

[MarkL]

Hello everyone.  I am not sure if you saw the Rigol response back.  If not here it is:

https://www.tequipment.net/assets/1/7/EEVBlog_message1.pdf

Thanks
Evan Cirelli

TEquipment.NET

Evan, at this point the 5us jitter is clearly not a trigger problem as concluded by Rigol in their letter.  And it also follows that their conclusion that it can be fixed in software is also not valid.  Even though they didn't see it, there are too many people seeing it now for them to hide from it, and it has nothing to do with self-cal or warm up.

It's possible that the problem could be fixed in software by loading different values into the ADF4360-7 PLL, but it could be also be a hardware problem with their loop filter design.

It's time to for Rigol weigh in on this with a real action plan.

[Bud]

So what would be a big deal to ask 2-3 people whose scopes have problems with jittef to ship them to Rigol for testing and reimburse shipping cost to those people. How much money would Rigol spend on shipping, $100 alltogether may be?

[(In)Sanity]

So what would be a big deal to ask 2-3 people whose scopes have problems with jittef to ship them to Rigol for testing and reimburse shipping cost to those people. How much money would Rigol spend on shipping, $100 alltogether may be?

The odds of Rigol not having either scopes in house already or access to scopes with this issue are slim to none.

Jeff

[alank2]

Do we have a summary yet of which scope models are affected by which issues?

You guys are talking about a specific PLL - which models have this?

I think it would make sense to identify each issue specifically.  Is the 5uS jitter where it gets bad, then better, then bad, then better at 5uS intervals a DS1000Z only issue or is that specific issue also present in the DS2K and/or DS4K?  On my DS4K I didn't see it get bad then better then bad then better, but it wasn't as good when the trigger is off screen, making that a separate type of issue.  I will take a look at my DS2K in a bit.

[jlmoon]

Do we have a summary yet of which scope models are affected by which issues?

You guys are talking about a specific PLL - which models have this?

I think it would make sense to identify each issue specifically.  Is the 5uS jitter where it gets bad, then better, then bad, then better at 5uS intervals a DS1000Z only issue or is that specific issue also present in the DS2K and/or DS4K?  On my DS4K I didn't see it get bad then better then bad then better, but it wasn't as good when the trigger is off screen, making that a separate type of issue.  I will take a look at my DS2K in a bit.

On my DS2202 (non A version) it did not make any difference where the trigger point was set.  I could pan from one area to the next still experiencing the same jitter.  When I switched to DC coupled trigger waveforms cleaned up as they should.  I did notice that as I went lower in frequency < 1Mhz the jitter was not as noticeable as when I raised the frequency towards 20Mhz.  I did not get to try anything higher than 20Mhz, but will later.
 

[pa3bca]

Just another one for the stats: My DS1074Z (thinking it is an 1104Z) that I bought abt 6 months ago does not have the N x 5us jitter problem at all.
It does have (as expected) the AC trigger coupling issue (as does my 2072A) but that is a long known bug. I never use AC trigger coupling so it does not bother me.

[MarkL]

So what would be a big deal to ask 2-3 people whose scopes have problems with jittef to ship them to Rigol for testing and reimburse shipping cost to those people. How much money would Rigol spend on shipping, $100 alltogether may be?

If I was Rigol, that's what I would do since they claim they haven't seen the issue.  That's why I was asking them for an action plan.

Mine is still in the 30-day eval period.  If the distributor or Rigol wants to send me a replacement unit, they can have this one to hack apart.

Do we have a summary yet of which scope models are affected by which issues?

You guys are talking about a specific PLL - which models have this?

I think it would make sense to identify each issue specifically.  Is the 5uS jitter where it gets bad, then better, then bad, then better at 5uS intervals a DS1000Z only issue or is that specific issue also present in the DS2K and/or DS4K?  On my DS4K I didn't see it get bad then better then bad then better, but it wasn't as good when the trigger is off screen, making that a separate type of issue.  I will take a look at my DS2K in a bit.

Sorry if that info got dropped... The one I've been testing with the 5us jitter issue is a DS1054Z, just arrived yesterday so it's factory fresh.  And yes, that's an accurate description of the problem.

A scan back through the thread should identify which other models have the 5us jitter problem.  There are several posts of screen captures at 5us delay intervals which is proof positive.

[dr.diesel]

I would be absolutely shocked if they truly can't reproduce the issue.  They are either still investigating, or unwilling to admit to duplication in fear of being forced to accept responsibility.