Advantest R6581 8.5 digit DMM mini teardown/repair

[Pipelie]

more results coming...

the linearity is not bad when using negative polarity input.

Maybe a good idea is to check the voltage PPM <> when you change polarity.

The calibration sticker show last calibration in 2005 valid for 10 years 
This instrument is in 2018 not calibrated during the last 13 years   

My DMM comes with manufacture's calibrated seal.

[Pipelie]

This is what I get on my R6581T:

turn off the AZ, and check again. or use a low output impendence voltage source to do the test.

[eurofox]

more results coming...

the linearity is not bad when using negative polarity input.

Maybe a good idea is to check the voltage PPM <> when you change polarity.

The calibration sticker show last calibration in 2005 valid for 10 years 
This instrument is in 2018 not calibrated during the last 13 years   

My DMM comes with manufacture's calibrated seal.

Calibration sticker 13 years ago ....

[eurofox]

This is what I get on my R6581T:

turn off the AZ, and check again. or use a low output impendence voltage source to do the test.

I just check it without AZ and get the same results.

[Kleinstein]

I just looked a little more in detail on the zero phase and especially the AZ capacitor. I might have found a possible source for nonlinearity:
During the measurement the bias of the OP (U205 = OP177) current charges the AZ cap. With something like a typical 1.2 nA into 35 nF during 200 ms this can be something around 7 mV. This voltage would alter the lower current sources during rundown, as there are only resistors for the currents. So this would result in a small error that depends on the rundown phase - so kind of some short scale wiggles or DNL type error.  However it should be a small error only: 10 mV applied for maybe 10 µs during rundown are only about 0.05 ppm of 10 V applied during 200 ms run-up.

So it might be a just visible error in a well working meter and C208 is probably well chosen. An offset adjustment at U205 might help with ultimate performance though.

[eurofox]

This is what I get on my R6581T:

turn off the AZ, and check again. or use a low output impendence voltage source to do the test.

I just check it without AZ and get the same results.

The pictures ...

[szszjdb]

Hi,  Mr.Kleinstein , Mr. Mickle T,
Thanks a lot!
The +5v of the U208 will not chang with the input, sure!  The c026 is 100p and found nearly no change when adding 50p on it in the negative bias test, why?

I found a cap broken on my old analog PCB , the C120 about 3.3nf, and replaced it with the similar one. And assembled back the analog PCB to my 6581 box. After done some bias test , it seems like the new analog PCB and even better than it. The Rin is about 2G in negative input and 11-22G  in positive input. Attached FYI.
Then I re-do the INL checking , the INL became much better than before.  The turnover check is also not so good ,but better than before. Please refer to the data in the INL test.
What is happen on it ?  I will double check the result tomorrow night. Attached also FYI , together with the new analog PCB INL test.

Best Regards,
szszjdb

[Kleinstein]

I can not locate C120 - but from the number I would guess it should be somewhere in the amplifier stage. A failing / wrong value cap could cause more ringing and this way problem on switching.

There is a chance that bending the board (e.g when removing the board) might change things. Especially ceramic caps can be sensitive. Connectors / pots might sometimes get better on movement. So it is possibly to somewhere have something like a cold solder joint, or band contact / cracked part.

Another thing that might change is the GND contact to the chassis. Ground loops over such contracts might be source for INL. However I would not expect such a blunder in der layout. However it may be that higher frequency "noise" / switching glitches to change, depending on the ground contact quality.

There is also the possibility that mechanical stress could effect some of the resistors and maybe also FETs (shift threshold). The longer Resistor networks like R201 or R213 might be somewhat sensitive, but that should not effect INL very much (more like DNL).

Adding 50 pF to C026 would slow down switching a little more, but this might not result in that much more trouble.
Reducing R083 would be a way to speed up the turn off, though at the cost of possible higher current spikes at the input.

The AZ mode leakage looks somewhat bad over the whole range and not just above a certain voltage like with the other board. One might have to look at the switching waveforms again, to see if the error is more like
- trouble with the guard
- too positive a gate voltage in some cases (e.g. from  amplifier ringing)
- cross conduction because off to slow turning off or too fast on

Cross conduction might be visible as current through R21, Pin 10 of the MUX.

The input current can be calculated over much shorter time frames (down to adjacent readings). This shows if the leakage is like a constant resistance or more like extra leakage above some threshold.  As far as I did calculations the resistance seems to be lower at high voltages.

[TiN]

C120 is film SMT cap near DG442DY by the left of the MUX hybrid.

I did a patch like Mickle.T. suggested to fix relay overheating issue, and now my meter have better matching for +FS/-FS on 10V range. E.g. my 792X reference (LTZ)
Positive 6581T: 10.0000118 V
Reverse 6581T: -10.0000158 V
Delta = 0.4 ppm.

I also compared firmware images from FTP and my unit (R6581_U102_EPROM0_27C4096_SIS004245_A02_sw.BIN and R6581_U103_EPROM1_27C1024_SIS004246_A02_sw.BIN, I assume these are from quarks) and they are binary identical. Perhaps T-version meter have different GAL/PAL ROM or strap resistor pullup/down to detect as "T" somewhere?

[Mickle T.]

I can not locate C120 - but from the number

Sorry, it's my bad C213.

I have a more fresh DMM with another firmware version numbering, but unfortunately I don't have EPROM reader

The answer from ADCMT apps engineer:

   Thank you for your inquiry.
   R6581T was presented to market as affiliated equipment for IC Test
System by ADVANTEST.
   Please contact and request for the data sheet with ADVANTEST.

 

[eurofox]

I can not locate C120 - but from the number

Sorry, it's my bad C223.


The answer from ADCMT apps engineer:

   Thank you for your inquiry.
   R6581T was presented to market as affiliated equipment for IC Test
System by ADVANTEST.
   Please contact and request for the data sheet with ADVANTEST.

 

I got a similar answer from ADCMT advising me to get in touch with Advantest in Europe.
I got an answer from the assistant of the general manager of Advantest asking Rohde & Schwarz to answer on my email with respect to the <> of R6581 & R6581T.

eurofox

[TiN]

Interesting thing I found on my 6581T. Diag mode values are not reported correctly:
DIAG INTERNAL Check ,
x1Zero_1 FAST = -0.0230 (OK)
x1Zero_1 PRECISION = +2.947131 V
x10Zero = +294.608 mV
x100Zero = +29.488 mV
7.2VREF = 10.0248870 V
-10VREF = -6.88450 V
-1VREF = -687.868 mV
-0.1VREF = -68.755 mV
Int_temp = +63.46 C
Current checks are not right either, most show around 6.88 ratio smth (e.g. 10uA is -6.885 uA)

[szszjdb]

Hi,  Mr.Kleinstein and  Mr. Mickle T,
Thanks a lot!

After re-checked the INL and used the 3458 as the reference, the INL looks more reasonable than yestoday. The err is max. 0.4ppm in the positive side for 6581 vs 0.1ppm for 3458. Attached FYI.

I have to mention that I have changed the Q102 and Q104 to U401 before beside replacing the C120. That might reduce the bias to the normal. 

Now the old analog PCB is more like the new one. I will check the timing of the control gate of the MUX tonight.


Best Regards,
szszjdb

[szszjdb]

Hi,  Mr.Kleinstein and  Mr. Mickle T,

Further test with the control gate of the MUX PIN17/PIN20/PIN10 with ADIN.  No odd point found.

I have also change the R83 from 10k to 68k or 1k and  can not find visualble change both in the waveform of the gate test and the negative discharge test . It seems the 10K is better in the case.

The photo No.1-3 are for PIN17/20 and No.5-8 are for PIN10 with 10k/68k of R83.  Attached FYI.

Would like to have your advice.

Best and Regards,
szszjdb

[Kleinstein]

The AZ-Back curves (no 5 and 7) show a significant overshoot for the amplifier output. This could cause the gate voltage on pin 20 to go well above the -10 V level and thus cause gate current to the input. I am afraid the capacitor is not enough to prevent this.  The data from Pin 20 for the back case should give that information.

I would not expect a significant larger resistor for R083 to work, as this would not allow the gate to go negative enough to fully turn off with a very negative input. If at all a slightly small value could help a little in some cases.

One could likely test the amplifier on it's own with a square wave signal at the input in non AZ mode. If there is a lot of ringing this should be fixed. Different FETs for Q102 could have an influence (e.g. higher trans-conductance and thus higher gain - which would be good for low noise, but could cause ringing). The speed of U104 could also be a factor to effect ringing - so some units might be better than others. If ringing is a problem one could likely improve on this.

The current to ground via pin 10 (e.g. pic 6) looks a about normal: first a positive peak due to the gate going positive (-18 V to around -12 V), so coupling through gate capacitance. After that the slightly negative values from charging the DCV amplifier and rest of MUX circuit. The initial negative peaks looks a bid big and might include some cross conduction, but it could be just due to the steeper slope. The final positive peak with ringing is a bit odd. It includes the gate voltage rising above the threshold. The ringing could be capacitive coupled from the DCV amplifier ringing.
The front edge curve is mainly the large peak from a fast gate discharge. The small lager wiggles are very small, so I don't think they would be relevant and may also be just noise pick-up.

Are those test with the PROTECT on (the extra capacitor at the input) ? This might be needed in AZ mode to reduce the current spikes to reach the output and this way react to odd things like cable lengths.

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks a lot!

All the test with the PROTECT off and GUARD low setting in AZ mode. I also notice something odd with the bigger noise in the reading when in INL test by resistor mode.The resistor string is powered by the LTZ10V with battery and the reading should have the same noise performance with LTZ10V(around 1uv), but sometime reached 5-6uv max.. So I was wondering if the protect cap will leading to that , then just turn off the PROTECT and set GUARD low, but no obvious change.  Anything missing?

Best Regards,
szszjdb

[eurofox]

I got better resistors for 1 and 10M ohm at 1% now, calibration is done internally that is certainly not the best.

1M ohm

range 1000K 1000.635
range 10M    1.000611
range 100M   1.00062
range 1G       1.00xx xx = not stable

10M ohm

range 10M    10.089
range 100M  10.089
range 1G       10.091

eurofox

[Kleinstein]

Hi,  Mr.Kleinstein,

Thanks a lot!

All the test with the PROTECT off and GUARD low setting in AZ mode. I also notice something odd with the bigger noise in the reading when in INL test by resistor mode.The resistor string is powered by the LTZ10V with battery and the reading should have the same noise performance with LTZ10V(around 1uv), but sometime reached 5-6uv max.. So I was wondering if the protect cap will leading to that , then just turn off the PROTECT and set GUARD low, but no obvious change.  Anything missing?

Best Regards,
szszjdb

Like with other amplifiers the input of the DMM will have some current noise, not just voltage noise. In the AZ mode there is a good chance the current noise can depend on the DC voltage. Near zero voltage might be s sweet spot. There is a good chance the higher than normal input current is also paired with higher than normal current noise. Having a noise in the 5 µV range with something like a 20-50 K input resistance would mean an input current noise in the 20-50 pA(eff) range. This would be quite a lot and quite poor with higher impedance sources.

The extra capacitor from the protect mode can help to reduce current spikes reaching the outside. So I would expect it to be better to have the Protect mode on when using the AZ mode - up to the point of having this as a requirement. I don't understand the naming for the Protect option - to me this is more a bit of input filtering. So I would expect some possible improvement with the protect on, but it seems to not help much.

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks a lot!

I checked the response of the DC amplifier at ADIN with square wave input and found normally with no ringing. Attached FYI.

The discharge test show that the Rin at 9V is about 1.87G, 1.25G and 0.62G , corresponding to the 10K, 1K and 68k value for R83.  So I said the 10K might be the best pair for the 100p.
Then I tried to add the C26 to 1Nf and found obvious improvement in the Rin  at 9v.  It reached 2G vs the old 1G at 9v point.  Attached also FYI.

Further waveform  test with the gate shows that the speed of the DCV gate is slow down. That might lead to the AZ switch opening before the DCV switch closing ,thus reducing  the current flow to the AZ resistor. Right?
But the waveform of the  back edge of the ADIN show more ringing. Is that OK?

Would like to have your further advice!

Best Regards,
szszjdb

[Kleinstein]

The square wave curve dues show quite some undershoot. However the ringing is not resolved to the low horizontal resolution. However there seem to be no overshoot - so it could be a problem on limiting, not just the (linear) compensation, which would be symmetric.
The picture ADIN(Y)_PIN20(R)_AZON_BACK-3.jpg also shows clear undershoot.  The odd thing is the gate voltage is still going up smooth, so the filtering with C026 seems to be enough.  A strong overshoot, that is not filtered out by C026 might be a problem, as it could cause leakage to the gate.  So far it looks like there is sometimes quite some overshoot, but C026 is still good enough to filter that out.
However things might be worse when doing current or resistance measurements: here there is not extra delay from C026 and thus trouble is expected with significant overshoot - this could for example be the cause of the trouble with the 1 M resistor measured in different ranges. So preferable there should be less ringing with the amplifier.

The odd thing is the ADIN_Back-3 curve showed today looks completely different (much better) to the tests before, when looking at pin 10 instead of pin 20. Looks like this curve is with a larger C026 and thus the FET turning on very slow so that there is less undershoot and less overshoot too.

The input current is highly voltage dependent. So it does not make much sense to show an effective resistance. I would take something like the slope of the discharge curve over a much smaller range (e.g. 2 readings) and give the current values for a few voltages to look at, like -8 V , - 5 V and - 3 V.

Again - R83 much larger than 10 K would not work as it would not allow to turn off at -12 V anymore. So if it needs to be a bit slower it would be about increasing C26. 1 nF is likely too large, but may be OK for a test. This test clearly showed that the is a kind of timing problem with the switching, as slower switching is causing less input current. However making C26 larger might solve the possible trouble on the "back slope", it could cause trouble at the front slope in that Pin 20 is turning off fast enough. So my guess would go towards a slightly larger c26 and slightly smaller R083  (e.g. 220 pF and 3.3 K). Thus the input channel would turn on a little slower due to C26 and turn off a little faster due to smaller C26*R083. In addition one might have to add a way to speed up the downward direction when the guard voltage is dropping fast. This could be something like 5 K and a diode ( kathode towards guard) in series between the guard (=pin28) and pin 20.

The test with the 1 nF cap seems to indicate that the problem is more with the back slope and not with the front slope.
However having 1 K for R083 also looks like a small improvement.
So there might be problems at both ends and also the overshoot problem is still possible with the original 100 pF in place.

I guess it would be a good idea to check a simulation of the input stage to get an idea of what performance to expect and where possible fixes for overshoot could be. For me that amplifier is a bit to complicated to do that on paper. relying on the compensation of the OP07 could be a problem though as it would requite a good model for that OP.

Edit:
I did a short simulation, but I still miss a suitable model for the U401. With 2N3819 used as JFETs, the circuit kind of works, but it shows a tendency to not so well behave when recovering from large steps. This would kind of supports the observed large overshoot after negative saturation and better behavior when in the linear range.

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks a lot!

The difference waveform of the AZ back edge is due to the 1NF cap, which smooth most of the overshot of the PIN20, the gate of the DCV control JFET.  Pls refer to the Photo 1 , the overshot reached for about 3V, which leading to large charge injection to the DCV channel.  When change C26 to 1NF, the overshot is reduced to around 0.8v, so reduce the effect of the gate charge injection. However it is small, it become forward biasing of the G-S or G-D.  That is normal?   Whcih might leading to the forward bias?  Pls refer to the Photo 3-5.

The best try of R83 is 10K from my testing. The front edge of AZ is not critical as the DCV channel turn off so fast and the gate of AZ JFET  turn on slowly due to the slow slope of the guard U107 output.

All the timing is same for the positive and negative input , so why there has huge different from the bias current ? Anything missing?

Best Regards,
szszjdb

[Kleinstein]

I did a simulation of the amplifier and also the switching parts. Though with different JFETs and slightly simplified is does gives curves rather similar to the measurement. However quite a few configurations refuse to simulate all the way and stop.

In the simulation there is some current from a forward biased gate ("pin 20") and it takes about a 1 nF to make the transition slow enough and shift the voltage for which this leakage occurs to about -8 V.  So this would suggest this behavior might be kind of normal and may not be due to a defect. The type of FET can also have an effect - so it might be the usually rather large parameter scattering with the JFETs that make some units work and some not so well.

As the curves look about the same, a would expect the extra input current due to the gated current due to forward bias during transition (Zero -> DCV with very negative input).

The weak point causing this is that the amplifier is relatively slow, especially the slew rate is limited by the OP07 (the one in the precision channel and the extra buffer for the guard). The limited slew rate and typical BJT input of the OP07 also makes the clamping diodes at the input less efficient: the OP reaches it's maximaum slew rate already at some 50 mV, well before the diodes come into action. This results in quite some overshoot when coming out of saturation, possibly even sustained oscillation (once triggered by a large step) in some cases of the simulation.

With this slow amplifier it would take something like C026 = 1 nF maybe even a bit more.  This would reduce the overshoot for the gate voltage enough.

A possible alternative could be exchanging the OP07s (U107 and U104) with some faster OPs. These OPs don't need to be super precise like the OP07.  U107 is just configured as a follower and should thus not cause problems with a somewhat faster type.

The simulation had no problem with a faster OP (LT1056 tested) for U104. So chances are, the real circuit could also work with a fast OP. Having a JFET OP for U104 would also result in the slew rate limit to be reached with a much higher input voltage and thus only after the diodes engage. At least in the simulations the amplifier worked much better with the LT1056 when coming out of saturation. I have not simulated the higher gain modes, but usually those should not be that critical.
I choose the LT1056 for the simulation because the models are included, but I would expect similar JFET based OP like TL071 to also work. The main point is to get a higher slew rate, not so much the higher GBW.
 
With the faster OP, the 100 pF value for C026 can be enough.

Attached are a picture of a simulation that corresponds to the file ADIN(Y)_PIN28(R)_AZON_BACK_1NF-2.jpg and the simulation model:

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks for the picture and simulation!

I have not got LT1056/TL071 in hand ,so I just change the U107 to opa209, which has the SR about 4V/us , 10 times above the OP07.  After checking the gate waveform, the strong ring is found on the back edge. Pls refer to the photo 1, it is still with the 1NF for C26  and have the chance to strongly forward bias the GATE to DRAIN for about 20us, where as the GATE to SOURCE is still zero bias. When changeing the C26 back to 100p, the gate start ringing and might leakage more to the DCV channel.  Can we suppose  that the reason for using the much slow OP07 is to prevent such ringing?

Best Regards,
szszjdb

[Kleinstein]

The OP209 is way faster than the OP07. Still it should be not problem for the follower (U107). However the input current might be a little high (especially in x 10 mode). Some ringing at the back end was seen before at ADin, when the voltage was so high that the output reached saturation. U107 is just a follower behind the main amplifier. The faster OP seems to contribute a little. This could be a little via capacitive coupling, and maybe by damping the feedback signal a little by the clamping diodes in the OP07 when it can't follow the slew rate.
However the main question if the amplifier itself will ring is more dependent on U104.

The ringing is not the normal type of ringing with a constant frequency, but is showing more like constant slew rate and thus higher frequency when the amplitude goes down. From what I see from the simulations, one problem with the amplifier is that the clamping with the diodes at the input of an BJT OP (U104) will activate too late. So C120 will charge up to far and cause ringing from a not well working anti-windup. This can cause a kind of nonlinear ringing. To a certain degree a large amplitude in ringing slows down the amplifier and too slow an amplifier can be a problem in that circuit too.

I don't know and don't understand why they choose the OP07 for U107. At first sight it is an odd choice for both places due to the very limited slew rate and also the input current. They use super low leakage CMOS switches for the gain and than a BJT based OP - that is odd, but OK since the differential input resistance is high enough for the OP07. The damping of the ringing with a slow U107 might be one reason, but I still think it is a poor choice, as it does not address the point that causes ringing in first place.  It only adds some filtering, but less effective as a larger C026.

For the main amplifier the OP07 makes some sense, as it has high gain and is about suitable for a source impedance of 40 K. However the OP07 is slow and how the amplifier looks, the second OP will not  increase the slew rate by much at gain 1. This OP sets the overall bandwidth, but I don't see a reason why it has to be so slow.

At least in the simulation a faster OP for the main amplifier even tends to reduce ringing. Here too much GBW could be a problem (e.g. due to capacitive coupling around the MUX), but the LT1056 simulated OK. This change in OP reduced ringing, despite of higher speed. Because of the high impedance, usually high slew rate and the clamping with the diodes a JFET OP is likely a good choice. For very good accuracy a high gain for that OP could be an advantage.  The input stage gives a gain of around 20-40 - so a very high noise level (e.g. > 200 nV/sqrt(Hz) at 2 Hz) could be a problem. So the choice of JFET OPs may not be that easy. Maybe they preferred the higher gain of the OP07 over higher speed.

To really speed up the amplifier one has to speed up U104 and U107. One slow amplifier would still limit the speed.

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks for so detail analysis. Very helpful!

I will try the TL071 tonight and get some LT1056 for testing later.

From the negative discharge testing , the larger the c26 is,  the larger the Rin is. But I found something odd with the 1N for c26, that the ZERO point will have larger offset like 1-2uv after calibration , where as in 100p conditon it is just around 0.5uv. So maybe the 100p or 350p will be better for all.
Attached FYI.

Best Regards,
szszjdb