Well you'll have no argument from me. Certainly 1% was a round number and, I agree, on the high side. Although I have encountered the odd discrepancy, I did not write it down, so if it makes you happier, assume the agreement is perfect until you find a counterexample
Again from the programmer point of view, using nothing but the Reference Manual and expecting to hit the right identifiers without needing to refer to the C header files, etc... this is generally successful, but the one which gets me most often is register groups. I.e. they could have implemented this using an array FOO[], or using names FOO1, FOO2, etc. and it's not always obvious from the manual. But this is a minor quibble.
I'm just lucky I wrote that duplicate example into my changelog (after stumbling over it) or it would have been lost forever. Your point is sound, who can remember this stuff in thousands of register names ?
I started this thread because I was genuinely trying to understand these differences I kept finding between C code and the CMSIS-SVD syntax.
I personally think the STM Reference Manuals are pretty good however the sheer numbers of documents one can have open for STM32 design can sure take up all the screen real estate!
At least CMSIS-SVD is XMl and allows the automatic creation of specialized documents to assist the programmer for any programming language. For me as a Forth programmer this is heaps easier than the usual bunch of header files for C. For instance I've included the SVD 'description fields' into my project files so I don't have to refer to the Reference Manual as much as I did at the start.
Without the CMSIS-SVD ( or a similar facility) Forth use on STM32 would have been near impossible.
Here is a Forth memmap example for RCC:
$40021000 constant RCC ( Reset and clock control )
RCC $0 + constant RCC_CR ( Clock control register )
RCC $4 + constant RCC_CFGR ( Clock configuration register RCC_CFGR )
RCC $8 + constant RCC_CIR ( Clock interrupt register RCC_CIR )
RCC $C + constant RCC_APB2RSTR ( APB2 peripheral reset register RCC_APB2RSTR )
RCC $10 + constant RCC_APB1RSTR ( APB1 peripheral reset register RCC_APB1RSTR )
RCC $14 + constant RCC_AHBENR ( AHB Peripheral Clock enable register RCC_AHBENR )
RCC $18 + constant RCC_APB2ENR ( APB2 peripheral clock enable register RCC_APB2ENR )
RCC $1C + constant RCC_APB1ENR ( APB1 peripheral clock enable register RCC_APB1ENR )
RCC $20 + constant RCC_BDCR ( Backup domain control register RCC_BDCR )
RCC $24 + constant RCC_CSR ( Control/status register RCC_CSR )
RCC $28 + constant RCC_AHBRSTR ( AHB peripheral reset register )
RCC $2C + constant RCC_CFGR2 ( Clock configuration register 2 )
RCC $30 + constant RCC_CFGR3 ( Clock configuration register 3 )
RCC $34 + constant RCC_CR2 ( Clock control register 2 )
A Forth bitfield example for RCC__AHBENR:
\ RCC_AHBENR (read-write)
: RCC_AHBENR_DMAEN %1 0 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_DMAEN DMA1 clock enable
: RCC_AHBENR_SRAMEN %1 2 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_SRAMEN SRAM interface clock enable
: RCC_AHBENR_FLITFEN %1 4 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_FLITFEN FLITF clock enable
: RCC_AHBENR_CRCEN %1 6 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_CRCEN CRC clock enable
: RCC_AHBENR_IOPAEN %1 17 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPAEN I/O port A clock enable
: RCC_AHBENR_IOPBEN %1 18 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPBEN I/O port B clock enable
: RCC_AHBENR_IOPCEN %1 19 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPCEN I/O port C clock enable
: RCC_AHBENR_IOPDEN %1 20 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPDEN I/O port D clock enable
: RCC_AHBENR_IOPFEN %1 22 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPFEN I/O port F clock enable
: RCC_AHBENR_TSCEN %1 24 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_TSCEN Touch sensing controller clock enable