EEVblog #683 - Rigol DS1000Z & DS2000 Oscilloscope Jitter Problems

[leppie]

I hope it fixes the issue on those units as well.

It did for me, and for poida_pie.

[Teneyes]

[Well, i've got DS2072 which i'm not sure will be a good idea to update now (working on some project now and don'w want to run into situation with untrusted scope...) That's my concern atm

 If you use AC triggering , then I would update the FW

Are there other issues discovered than the two in the first message in your topic? If not, they seems to not be critical for me and i'll be able to give it a shot with update next week.

  Who knows if there are more
  I have found a Limit , that is more funny than a fault that I will be posting next.

[MarkL]

Confirmed fixed 5us and AC coupling jitter on my unit.
Here are before and after PLL output shots.
Have done a video on it.

I did a little math on the FM modulation in these two screen shots.

On the pre-upgrade, I'm getting a pk-pk jitter of 700ps.  Looking at the video, that seems to be in the ballpark, but I think the video looks slightly more jittery and may be due to other contributions such as trigger jitter.

Post-upgrade I'm getting about 45ps, so that's quite an improvement.  It won't be visible even at the highest sweep speeds on this scope.  Also as shown in the video.

The PLL still is not locked, but it looks like Rigol has found a set of parameters to keep it from flapping in the breeze.


Bud: The DS1054Z owner I mentioned has agreed to allow me to pop the back off his unit to do some measurements on the clock before and after upgrade (as long as he can do it with me).  I don't expect to find anything other than what Dave and others have shown so far, but I will also take the opportunity to heat and cool the PLL and surrounding area to see what happens.

And I might take a stroll around the power pins again.  Perhaps all academic at this point, but I'm curious what's throwing 67.5kHz in there.

I can also capture the PLL programming bytes if you're interested in the seeing what they've set in the new firmware version.  Or if not, and this is a dead issue for you, let me know.

Most users apparently deem it to be "good enough" for their purposes, and that saves Rigol from a painful hardware recall that would probably crush any slim margin they had.

I'm expecting at some point Rigol will fix the loop components in manufacturing, and quietly increment the board rev. The firmware will load new PLL register values to match the updated loop filter on those boards.  But given their modus operandi, we'll never know.  Users == mushrooms.

[DanielS]

I'm expecting at some point Rigol will fix the loop components in manufacturing, and quietly increment the board rev. The firmware will load new PLL register values to match the updated loop filter on those boards.  But given their modus operandi, we'll never know.  Users == mushrooms.

We WILL know - someone is bound to notice PCB rev 1.2 or whatever it ends up being sooner or later and then others, if not the OP, will investigate.

Whether people will still be tracking issues/progress on the 1000z by then is a different story.

[orin]

Confirmed fixed 5us and AC coupling jitter on my unit.
Here are before and after PLL output shots.
Have done a video on it.

I did a little math on the FM modulation in these two screen shots.

On the pre-upgrade, I'm getting a pk-pk jitter of 700ps.  Looking at the video, that seems to be in the ballpark, but I think the video looks slightly more jittery and may be due to other contributions such as trigger jitter.

Post-upgrade I'm getting about 45ps, so that's quite an improvement.  It won't be visible even at the highest sweep speeds on this scope.  Also as shown in the video.

The PLL still is not locked, but it looks like Rigol has found a set of parameters to keep it from flapping in the breeze.


Bud: The DS1054Z owner I mentioned has agreed to allow me to pop the back off his unit to do some measurements on the clock before and after upgrade (as long as he can do it with me).  I don't expect to find anything other than what Dave and others have shown so far, but I will also take the opportunity to heat and cool the PLL and surrounding area to see what happens.

And I might take a stroll around the power pins again.  Perhaps all academic at this point, but I'm curious what's throwing 67.5kHz in there.

I can also capture the PLL programming bytes if you're interested in the seeing what they've set in the new firmware version.  Or if not, and this is a dead issue for you, let me know.

Most users apparently deem it to be "good enough" for their purposes, and that saves Rigol from a painful hardware recall that would probably crush any slim margin they had.

I'm expecting at some point Rigol will fix the loop components in manufacturing, and quietly increment the board rev. The firmware will load new PLL register values to match the updated loop filter on those boards.  But given their modus operandi, we'll never know.  Users == mushrooms.

I'm going to play Devil's advocate and say "Define locked".  There is always some variation in the VCO control voltage in a PLL.  No-one has yet said what it is with the new firmware.  If it's obviously bouncing off its limits, it's obviously unlocked.  Not hitting the limits?  Is it locked?  Where do you draw the line?  We don't even have the chip itself's opinion as to locked/unlocked yet.

We are going on speculation from FFTs that are unearthing artifacts from beneath the noise level.  Remember that it's an 8-bit ADC.  You have 40-odd dB dynamic range and the FFTs I have posted are showing artifacts at worst -70dBc.  It is taking IMO heroic efforts to unearth these artifacts.

For sure, there are some spurs, but realistically, they will not show on the scope's builtin FFT.  I couldn't see any of them on the scope's FFT for the plots from Alessandro's program that I posted.

Now with the new FW, I was seeing some ringing on my GPSDO's waveform when using minimum persistence.  I thought it was perhaps due to the scope.  But merely unscrewing the fasteners on the box containing the GPSDO made the ringing go away.  Is it the scope?  Opinions?  (It's not visible on my TDS-210, but it does not have the persistence the Rigol has, so not surprising.)  It needs further investigation for sure.

Finally, FWIW, it is a good idea to set the trace to 'dots' rather than 'vectors' to see what is really going on (or not) with a waveform.  The sin(x)/x interpolation can get confused and show ringing that isn't really there.  Certainly, it happened with my GPSDO's output (which is fairly square) when I enabled a second channel and the sample rate dropped to 500K.  There was suddenly ringing before the falling edge that wasn't there before.  Set the trace to 'dots' and no signs of ringing.

Orin.

[tautech]

Confirmed fixed 5us and AC coupling jitter on my unit.
Here are before and after PLL output shots.
Have done a video on it.

The PLL still is not locked, but it looks like Rigol has found a set of parameters to keep it from flapping in the breeze.


Bud: The DS1054Z owner I mentioned has agreed to allow me to pop the back off his unit to do some measurements on the clock before and after upgrade (as long as he can do it with me).  I don't expect to find anything other than what Dave and others have shown so far, but I will also take the opportunity to heat and cool the PLL and surrounding area to see what happens.

And I might take a stroll around the power pins again.  Perhaps all academic at this point, but I'm curious what's throwing 67.5kHz in there.

I can also capture the PLL programming bytes if you're interested in the seeing what they've set in the new firmware version.  Or if not, and this is a dead issue for you, let me know.

With all the good work you have done it would be a shame not to also record these measurements for prosperity. 

[tggzzz]

Finally, FWIW, it is a good idea to set the trace to 'dots' rather than 'vectors' to see what is really going on (or not) with a waveform.  The sin(x)/x interpolation can get confused and show ringing that isn't really there.  Certainly, it happened with my GPSDO's output (which is fairly square) when I enabled a second channel and the sample rate dropped to 500K.  There was suddenly ringing before the falling edge that wasn't there before.  Set the trace to 'dots' and no signs of ringing.

Yes, that is my preference too.

I have seen a related effect on an Agilent scope set to infinite persistence. I was comparing a digital and 70s analogue scope and looking at the signal integrity of a fast digital edge. With vectors on I saw a surprisingly wide "envelope" of the maximum variation. With points the "excess variability" disappeared and the envelope was as expected and very similar to that seen on the analogue scope.

A good example of the subtle problems that can be introduced by digital scopes, and that you shouldn't blindly accept what you see. Scopes can lie.

[Bud]

I second that, but I use dots for realistic appreciation of noise, or crap for that matter while we are on this topic.

[Bud]

Bud: The DS1054Z owner I mentioned has agreed to allow me to pop the back off his unit
..
I can also capture the PLL programming bytes if you're interested in the seeing what they've set in the new firmware version.

That's terrific, lets do it. The owner should be jumping and screaming from being so happy  to have such a truly engineering opportunity to learn.
If have time try to do and compare a few Math functions , i.e. signal add/subtract, to see if there was a noticeable improvement noise-wise and accuracy.

I'm expecting at some point Rigol will fix the loop components in manufacturing, and quietly increment the board rev.

I am not.

[Bud]

I'm going to play Devil's advocate and say "Define locked".  There is always some variation in the VCO control voltage in a PLL.  No-one has yet said what it is with the new firmware.  If it's obviously bouncing off its limits, it's obviously unlocked.  Not hitting the limits?  Is it locked?  Where do you draw the line?  We don't even have the chip itself's opinion as to locked/unlocked yet.

In Beta Rigol changed PLL programming to enable the lock detect pin. I would expect it to be also enabled in this release. We will look at the programming data and wil know this, then it will be a matter of checking the pin with a multimeter.

For sure, there are some spurs, but realistically, they will not show on the scope's builtin FFT.  I couldn't see any of them on the scope's FFT for the plots from Alessandro's program that I posted.

What people still do not seem to be alerted by is the modus operandi of this company. I pointed out before to the facts they blindly copy designs between device models, not reading datasheets and not honoring the manufacturer's specifications, overclocking the chips, tried to hide tracks of it by lasering the chip markins off. The level of engineering negligence and incompetency is stunning. If they could not get this building block right, where is a guarantee the rest of the system was built right ?

There is an analogy in Ham Radio world which is a company called MFJ. They too produce garbage but because it is so cheap , sales are good and every Ham and its dog buy their junk.

[EEVblog]

What people still do not seem to be alerted by is the modus operandi of this company. I pointed out before to the facts they blindly copy designs between device models, not reading datasheets and not honoring the manufacturer's specifications, overclocking the chips

To be fair, it appears as though the overclocking of the ADC was a deliberate strategy that pays dividends big time for them. Remember, Rigol were the first new company to come along and give affordable 1GS/s ADC sampling in a scope, and this is how they did it. There probably was no other easy way at the time?

tried to hide tracks of it by lasering the chip markins off.

That's called IP protection, no deliberate covering up of deliberately bad design work.

There is an analogy in Ham Radio world which is a company called MFJ. They too produce garbage but because it is so cheap , sales are good and every Ham and its dog buy their junk.

The market wants what the marker once.
Name another manufacturer that gives close to the same innovation Rigol offers for the price?

[rf-loop]

To be fair, it appears as though the overclocking of the ADC was a deliberate strategy that pays dividends big time for them. Remember, Rigol were the first new company to come along and give affordable 1GS/s ADC sampling in a scope, and this is how they did it. There probably was no other easy way at the time?

Only reason for use 40MSPS classified Analog Devices AD9288  chips was reduce manufacture cost for earn more.
It is exactly same AD9288  what can buy 40, 80 and 100 MSPS.  These chips are designed and manufactured for 100MSPS.
Then there is set of limits. From process they get different quality of chips. There is nothing wrong to run 40MSPS classified chips for 100MSPS. But who do this he must understand that datasheet specifications are not anymore valid. If this is not problem then go on.
In time when Rigol start this model they can buy 100, 80 or 40MSPS. But price is different.
If Rigol look that 40MSPS classified AD9288 meet Rigol needs (reduced specs) then there is not any kind of problem. They work as Rigol specs for Rigol customers.  What is overclocking or "overclocking" in this case - this discuss I do not want start anymore agen.

Only reason for 40MSPS chips was price!  Same AD9288 quaranteed meet 100MSPS specs limits was also available fom AD.
-40 chips price is 1/3 what is -100 chips. 15$ only for ADC chi.ps is better than 50$ when whole scope manufacturing costs need keep well under 200$ and there really is also other costs than just ADC chips..  Using these 40MSPS selected chips for 100MSPS meets Rigol own specified needs so theere is not any kind of problem use these. (of course in this case AD datasheet some specs are not valid - mainly perhaps  in ADC  input T/H circuit. leading poor SNR, SINAD, ENOB. If they meet still Rigol needs it is all what neeed)


About grinding chip label...  what is problen there. Nothing. Design belongs to designer and he can hide everything he want.  Many big brands haave done this as far as I remember. Not just grinding labels, also using wrong labels, also using more or less secret and later leaked manufacturer own classified codes lists for internal use.  Result with consumer eyes is same...
If I buy chips from  manufacturer and  I want they print my own part number there, I pay and they do. Say example I use AD9288.   I grind all label off   or  other case I have there my own label: JvwLMmwPbCR57Qx3. What is difference?
 
Other question is what they think they win with grinding or false marking any this kind of component. Who really want and need know, he know. It did not hide anything important example from manufacturers in china who are competitors. Who really think that time when DS1052E was launched manufacturer engineers in China did not know how to do this kind of interleaved ADC for cheap oscilloscope. Really there was not any secret innovations. This was circulating even in school boys exercises.  (only what they perhaps try hide they was selected this lowest grade 9288).

[EEVblog]

Only reason for 40MSPS chips was price!  Same AD9288 quaranteed meet 100MSPS specs limits was also available fom AD.
-40 chips price is 1/3 what is -100 chips. 15$ only for ADC chi.ps is better than 50$ when whole scope manufacturing costs need keep well under 200$ and there really is also other costs than just ADC chips.. 
Using these 40MSPS selected chips for 100MSPS meets Rigol own specified needs so theere is not any kind of problem use these. (of course in this case AD datasheet some specs are not valid - mainly perhaps  in ADC  input T/H circuit. leading poor SNR, SINAD, ENOB. If they meet still Rigol needs it is all what neeed)

Bingo.
Rigol were the first company to build a decent 1GS/s scope down to the price point we are familiar with today.
Part of the reason they were able to do that is very likely that they were able to shoe-horn the lower cost parts into the job, and to do it successfully.
Name another company that did this at the time, I'm willing to bet you can't.
Rigol lead the way, others followed.

Who really think that time when DS1052E was launched manufacturer engineers in China did not know how to do this kind of interleaved ADC for cheap oscilloscope. Really there was not any secret innovations.

Sure but the fact remains that no one actually produced an commercial quality product like this at this price point before Rigol did.

[rf-loop]

Only reason for 40MSPS chips was price!  Same AD9288 quaranteed meet 100MSPS specs limits was also available fom AD.
-40 chips price is 1/3 what is -100 chips. 15$ only for ADC chi.ps is better than 50$ when whole scope manufacturing costs need keep well under 200$ and there really is also other costs than just ADC chips.. 
Using these 40MSPS selected chips for 100MSPS meets Rigol own specified needs so theere is not any kind of problem use these. (of course in this case AD datasheet some specs are not valid - mainly perhaps  in ADC  input T/H circuit. leading poor SNR, SINAD, ENOB. If they meet still Rigol needs it is all what neeed)

Bingo.
Rigol were the first company to build a decent 1GS/s scope down to the price point we are familiar with today.
Part of the reason they were able to do that is very likely that they were able to shoe-horn the lower cost parts into the job, and to do it successfully.
Name another company that did this at the time, I'm willing to bet you can't.
Rigol lead the way, others followed.

Who really think that time when DS1052E was launched manufacturer engineers in China did not know how to do this kind of interleaved ADC for cheap oscilloscope. Really there was not any secret innovations.

Sure but the fact remains that no one actually produced an commercial quality product like this at this price point before Rigol did.

Exatly, they did it first so that it was ready product on the market in this price range (1)  with its features.

(1)

Rigol launches DSO, MSO, and AWG instrument lines
Test Measurement World Staff - December 18, 2008

Adding to its family of digital storage oscilloscopes, Rigol Technologies offers the DS1102E, which
delivers a bandwidth of 100 MHz, a real-time sampling rate of up to 1 Gsample/s, and as much as 1
million points of long memory depth on a single channel. The DS1102E costs only $795, and a 50-
MHz model, the DS1052E, costs just $595.

[kerrsmith]

Just a quick update on my scope.

I have now applied the new firmware to my scope after watching Dave's and Mad's (EcProjects) videos and it installed just like theirs did - it did not take long but waiting for it to finish whilst all the time hoping not to have a random power cut is quite hard.

I did not really have the 5us jitter but I did have the AC trigger issue, this now appears fixed as shown in the two images attached.

[MarkL]

...
The PLL still is not locked, but it looks like Rigol has found a set of parameters to keep it from flapping in the breeze.
...

I'm going to play Devil's advocate and say "Define locked".  There is always some variation in the VCO control voltage in a PLL.  No-one has yet said what it is with the new firmware.  If it's obviously bouncing off its limits, it's obviously unlocked.  Not hitting the limits?  Is it locked?  Where do you draw the line?  We don't even have the chip itself's opinion as to locked/unlocked yet.

I would define "locked" as whatever AD defines for their chip.  You get two choices (LDP = Lock Detector Precision):

When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns.

With LDP set to 1, five consecutive cycles of less than 15 ns phase error are required to set the lock detect. It stays set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle.

Take your pick.  Rigol set LDP=0 for the original firmware and the beta but I don't think they look at it anyway.

We are going on speculation from FFTs that are unearthing artifacts from beneath the noise level.  Remember that it's an 8-bit ADC.  You have 40-odd dB dynamic range and the FFTs I have posted are showing artifacts at worst -70dBc.  It is taking IMO heroic efforts to unearth these artifacts.

Not speculation at all.  I proposed the FFT approach because it was a method that could uncover the nature of the ADC clock without having to open the case, and without having special equipment.  It was shown earlier that the FFTs match the measured ADC clock, and mathematically the artifacts from the clock are appearing at the correct signal levels in the FFT.

In other words, it wasn't a heroic search for an FFT case that would make the scope look bad, if that's what you mean.  The external FFT is used as a tool to look at the ADC clock over a larger number of scopes than just the one I had here.

For sure, there are some spurs, but realistically, they will not show on the scope's builtin FFT.  I couldn't see any of them on the scope's FFT for the plots from Alessandro's program that I posted.

I agree 100% you'll never see it on Rigol's built-in FFT.  They don't use nearly enough points.  A Rigol document states 600 for the DS1000E/D/B/CA series and the Z series looks about the same to me.  In general, I think they need to up that by at least a magnitude to make the FFT more useful (and it still won't show the clock aberrations).

[Bud]

Rigol set LDP=0 for the original firmware and the beta but I don't think they look at it anyway.

HP/Agilent put LEDs on the boards to indicate the status of the power supplies and processors. This allows to instantly disgnose high level problems by checking the LEDs, in some cases by merely peeking through the case openings. Rigol did not bother even adding a test point for the PLL lock indication. If PLL is used in a circuit, the designer better go add an alarm LED or monitor the lock detect semaphor with the main processor. I'd think a check should be performed as part of the power up self check routine.

[Totalsolutions]

Thanks to CIDCORP for asking about the location of the update file location, I was looking everywhere and thought it was my ignorance but you jumped in first with the question. Have now updated my Rigol DS1074Z and can confirm several observations, first the boot time both before and after is 36.28 seconds. I have no jitter to speak of at least to my limited experience with digital scopes only have the inbuilt limited 15Mhz square wave (have 20Mhz sine wave) at 5us offset or any other sub-multiple (is that correct).  However the AC trigger coupling did effect my scope. I "upgraded" to 00.04.02.SP4. All "hacks" still in place and boot times identical. Jitter still OK and AC trigger fixed. HOWEVER, I now have Board Version upgraded to 4.1.1. The model was changed from DS1074Z to DS1104Z last December with the "hacks" applied, so what gives with the Board Version change, no one has mentioned here.

Paul

[AlessandroAU]

We are going on speculation from FFTs that are unearthing artifacts from beneath the noise level.  Remember that it's an 8-bit ADC.  You have 40-odd dB dynamic range and the FFTs I have posted are showing artifacts at worst -70dBc.  It is taking IMO heroic efforts to unearth these artifacts.

Its a common misconception that the noise floor of an FFT is limited to the SNR of the ADC. You must consider a 'FFT process gain"

My post from another topic:

Fair enough the dynamic range is not that high, but its definitely possible to have a noise floor at -130ish with 24mpoints (by zooming in). However I concede that the best dynamic range appears to be around 105dBm, which is still very good.

Also, just to show that is possible to take measurements exceeding 8 bits limit; Look at image 3, the scope is set to 5v/div or 40v max range. A 10mv pk-p signal is applied.

This is 20*log10(0.01/40) = -72db below full scale, a full 22db or so below the 8 bit resolution limit. Even though the waveform looks like barely like anything, thanks to the mathematics of the Fourier transform this signal is still measurable. Very neat!

Edit:
The tektronix MDO series also only uses an 8bit adc internally but has a DANL of -130dbm from 50khz to 5mhz (http://www.tek.com/datasheet/mdo4000/mdo4000b-series-datasheet-0) so it is definitely possible approach this kinda of performance with 8 bits.

also see: https://www.google.com.au/url?sa=t&rct=j&q=&esrc=s&source=web&cd=22&ved=0CC4QFjABOBQ&url=http%3A%2F%2Fwww.tek.com%2Fdl%2F48W-28882-2%252520%252520%252520MDO%252520Performance%252520WP_.pdf&ei=p_2YVOHwJcLZ8gWIsoKABg&usg=AFQjCNHaLpRkqk9Fxl4CPInDNz58hWFfLQ&sig2=vefpuXdZKo0KQWZVw9PI1g&bvm=bv.82001339,d.dGc&cad=rja

Edit:

Also see last pages of this analogue devices whitepaper http://www.analog.com/static/imported-files/tutorials/MT-001.pdf

[orin]

We are going on speculation from FFTs that are unearthing artifacts from beneath the noise level.  Remember that it's an 8-bit ADC.  You have 40-odd dB dynamic range and the FFTs I have posted are showing artifacts at worst -70dBc.  It is taking IMO heroic efforts to unearth these artifacts.

Its a common misconception that the noise floor of an FFT is limited to the SNR of the ADC. You must consider a 'FFT process gain"

My post from another topic:

Fair enough the dynamic range is not that high, but its definitely possible to have a noise floor at -130ish with 24mpoints (by zooming in). However I concede that the best dynamic range appears to be around 105dBm, which is still very good.

Also, just to show that is possible to take measurements exceeding 8 bits limit; Look at image 3, the scope is set to 5v/div or 40v max range. A 10mv pk-p signal is applied.

This is 20*log10(0.01/40) = -72db below full scale, a full 22db or so below the 8 bit resolution limit. Even though the waveform looks like barely like anything, thanks to the mathematics of the Fourier transform this signal is still measurable. Very neat!

Edit:
The tektronix MDO series also only uses an 8bit adc internally but has a DANL of -130dbm from 50khz to 5mhz (http://www.tek.com/datasheet/mdo4000/mdo4000b-series-datasheet-0) so it is definitely possible approach this kinda of performance with 8 bits.

also see: https://www.google.com.au/url?sa=t&rct=j&q=&esrc=s&source=web&cd=22&ved=0CC4QFjABOBQ&url=http%3A%2F%2Fwww.tek.com%2Fdl%2F48W-28882-2%252520%252520%252520MDO%252520Performance%252520WP_.pdf&ei=p_2YVOHwJcLZ8gWIsoKABg&usg=AFQjCNHaLpRkqk9Fxl4CPInDNz58hWFfLQ&sig2=vefpuXdZKo0KQWZVw9PI1g&bvm=bv.82001339,d.dGc&cad=rja

Edit:

Also see last pages of this analogue devices whitepaper http://www.analog.com/static/imported-files/tutorials/MT-001.pdf

I did say I was playing "Devil's advocate" at one point

Perhaps I exaggerated a little using the word 'heroic', but getting the NI drivers and libraries installed to run your program is far from trivial.  My point really is that in regular use of the scope as a time domain instrument, you won't see these 'artifacts'.

As for the signal at 100MHz plot, I should probably have done that at 50MHz since my scope is an unmolested DS1054Z.  Still, the scope still had enough response at 100MHz for the purpose.

Thanks for that last link BTW.

[MarkL]

My post from another topic:

...
Edit:
The tektronix MDO series also only uses an 8bit adc internally but has a DANL of -130dbm from 50khz to 5mhz (http://www.tek.com/datasheet/mdo4000/mdo4000b-series-datasheet-0) so it is definitely possible approach this kinda of performance with 8 bits.

Shahriar did a great review of the MDO internal operation and sensitivity tricks:

  http://thesignalpath.com/blogs/2014/03/17/tektronix-mdo4104b-6-mixed-domain-oscilloscope-mdo4000b-review-and-experiments/

Getting OT, I know.

[Bert Camper]

@AlessandroAU,

Thanks for pointing this out and for the link!
If I understand it right, this makes it possible to do distortion measurements 0.1% and below on audio amplifiers. Would be great!

--Bert

[rf-design]

I agree mostly. If the "fixed" firmware was installed from the start then nobody would have noticed the jittery PLL. If there are still problems or other artifacts then Rigol will lose some face and sales.

Exactly, just like no one knew or cared about the ADC overclock until it was discovered. And then the mud sort of stuck to Rigol, but it didn't affect the scope sales in any measurable way AFAIK. Some mud will stick because of this, but unless it proves to go sour again, I don't think it will hurt them or their sales.
It probably needs a few months of stats at least to see. But not everyone has the capability to test the clock, or desire to break their warranty seal, and that could potentially still be a problem for Rigol.
If they are smart they will get a hundred units and get the spectrum of the clock on each one, and do it over temperature.

There has been comfirmation of temperature sensitivity by 3 members pre latest firmware.
https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg577560/#msg577560
Does it still exist now, as yet it is another unkown.

I have previously reported temperature sensitive jitter related to guite long trigger delay times. (in my unit have not seen this "5us" (and multipliers) special jitter.  This long delay jitter was with all delay times (best visble over 50~100us delays) . It was with cold scope and then disappear after some minute warming and then start agen after warm up continue more some more minutes.

** This jitter I can not find in my individual DS1074Z at all  after update. 

** AC trigger jitter and position shift:  well fixed.

(Sidenote: And this is natural. With longer trigger delay, example with 100ms delay there is nearly 10ns "walking and jumping  around". This is natural amount of cheap oscilloscope cheap reference oscillator instability. (in my measurement 10second watching time peak to peak roughly around 1ppm after oscilloscope was well temp stabilized.)

I have designed many integrated PLLs over two decades. The first designs are based on external loop filter components. The latest are fully integrated and with programmable PI factors with special methods to overcome PVT effects on the loop parameters.

From this expierence I would argue that if there are temp issues these will come from the PLL chip. I could be that the PLL chip requires some tricks not stated in the application note but typical told on phone after a painful board integration phase. I would not say that in this case but it is not untypical. Bob Pease call it at a conference that the target for community analog IC designs is zero-phone call designs.

[kerrsmith]

Here are two FFT comparisons created very kindly by MarkL for me, they are of before and after the firmware upgrade. The signal used was from the XTAL2 pin on the ATMega328P chip.

The first two are from my bought Arduino attached to the computer.

The second two are from my homemade Arduino on proto board and powered from a 9V battery (via an LM7805 regulator).

Both FFTs have improved after the firmware upgrade.

[QuadFritz]

Hello-

Just got a message from my very friendly vendor (have my scope 1054z for roughly 3 weeks and asked immediately what about warranty vs jitter issue) that there is an update for download available BUT if the update for some reason fails it is NOT COVERED- I.e. repair will have to be paid!! 

So what kind of service is THAT? I am willing to fix the issue with their firmware (saving them a lot of shipping costs) and will have to pay the repair if it fails?

Anyways- what you get for the money scope wise is awesome and should not be forgotten!