EEVblog #683 - Rigol DS1000Z & DS2000 Oscilloscope Jitter Problems

[EEVblog]

To abuse the car analogy some more, it's like your car has a shimmy that you can't feel at 70 mph on the freeway, but at 100 mph on the track, it becomes obvious.  In normal use, driving to work, going to the grocery store, going on vacation, you'd never know it was there.

Poor analogy. Cars are mechanical things that can get worse with time, a shimmy may cause eventual self destruction of a part. Electronics doesn't generally do that. If it works now it'll likely still work exactly the same in 10 years time. Subject to temp variation and component aging.

[orin]

To abuse the car analogy some more, it's like your car has a shimmy that you can't feel at 70 mph on the freeway, but at 100 mph on the track, it becomes obvious.  In normal use, driving to work, going to the grocery store, going on vacation, you'd never know it was there.

Poor analogy. Cars are mechanical things that can get worse with time, a shimmy may cause eventual self destruction of a part. Electronics doesn't generally do that. If it works now it'll likely still work exactly the same in 10 years time. Subject to temp variation and component aging.

I said 'abuse' the analogy.  Forget about aging - just about what is happening now.  Any car analogy is flawed for the reasons you state.

[EEVblog]

Forget about aging - just about what is happening now.

I am. All evidence so far shows shows Rigol have fixed the problem. Unless more evidence or productions variation comes to light in the future, then that's the end of it.

[orin]

Forget about aging - just about what is happening now.

I am. All evidence so far shows shows Rigol have fixed the problem. Unless more evidence or productions variation comes to light in the future, then that's the end of it.

I agree.

[_Wim_]

Forget about aging - just about what is happening now.

I am. All evidence so far shows shows Rigol have fixed the problem. Unless more evidence or productions variation comes to light in the future, then that's the end of it.

I also fully agree. I purchased a 1054z also (has not arrived yet), even before the fix was known but the when problem was already discovered. When comparing this scope with other scopes in the same price range, in my opinion it still came out way ahead even with the jitter. And now that Rigol has provided a workaround, I do not understand what people still are complaining about.

Other scopes in this price range sometimes suffer from a very buggy software, lack of features, and those take years to be fixed, if ever at all, and yet people still recommend these based on bang for buck. But when a scope has good software and hardware to start with, but only has internally a hardware workaround, seems suddenly not a good product anymore?

Yes, Rigol made a mistake (as we all do in our jobs), and next provided a workaround instead of a fix to prevent a recall (which we all would try to do also). For me, I am glad that they were able to solve it this way, so that they can keep their fantastic prices. The cost of a worldwide recall would probably raise the price of this scope and future products, and people would still complain about having to miss there scope for many weeks until it is fixed...

[Bud]

@ Bud
Do you imagine the HW & Firmware settings Rigol has used to impact on possible ADF4360-7 failure in the future?

Sorry tautech, I do not understand the question, can you explain ?

[Muttley Snickers]

From what I have read here it look's like this subject is almost ready for bed, but as I am ready to purchase one and did ask in another thread as to whether it was worth waiting to see if hardware changes to the PLL circuit would be implemented. The consensus was that it's all good and why bother waiting.

But after reading some of the latest posts in this thread another question comes to mind and that is hypothetically, if changes were made to the PLL hardware would later FW revisions then have to be split into pre and post hardware changes or could a single FW cover both or all HW versions.

Please forgive my un- qualified posting on this subject.

Muttley

[aargee]

MuTitles, I'd go an buy one. You could be waiting forever for something that possibly won't happen for this generation of Rogol scopes. Mine is working fine with the new firmware, actually, it was working fine for me with the jitter - it was something I probably wouldn't have run into.
There seems to be a bit of driving of this issue by others for what end I can only imagine.

Dave's comment says it succinctly a few posts back. The issue is over unless someone can show the Rigol not performing to published specifications of the DSO.

[EEVblog]

But after reading some of the latest posts in this thread another question
comes to mind and that is hypotheticaly, if changes were made to the PLL
hardware would later FW revisions then have to be split into pre and post
hardware changes or could a single FW cover both or all HW versions.

Yes, they would almost certainly need different PLL coefficients for different hardware revisions. But given that the PLL is programmed by the actual micro source code and not by the firmwar bit file it's fairly easy for them to add the code that hold the coefficients for different hardware and then detects and programs as appropriate on boot up.

[Monkeh]

@ Bud
Do you imagine the HW & Firmware settings Rigol has used to impact on possible ADF4360-7 failure in the future?

Sorry tautech, I do not understand the question, can you explain ?

He's asking if you believe the lifetime of the IC could be affected by operating under these conditions. Can't see it, myself.

[tautech]

@ Bud
Do you imagine the HW & Firmware settings Rigol has used to impact on possible ADF4360-7 failure in the future?

Sorry tautech, I do not understand the question, can you explain ?

He's asking if you believe the lifetime of the IC could be affected by operating under these conditions. Can't see it, myself.

Correct Monkeh
Just wondering.....if (as Bud has identified) it's operation OUTSIDE manufacturers recommendations might impact on the IC's MTBF.
Anybody put a IR temp gun on it to see if it's running hot?

[kwass]

Just FYI:

I've started a bug report/wish list thread for the next firmware release for the DS1000Z here:

https://www.eevblog.com/forum/testgear/rigol-ds1000z-series-%28ds1054z-ds1074z-ds1104z-and-s-models%29-bugswish-list/

I'm carefully reading all the posts and gathering up the reports/comments in the top post.  Hopefully Rigol will keep an eye on it.

-Katie

[DanielS]

if changes were made to the PLL hardware would later FW revisions then have to be split into pre and post hardware changes or could a single FW cover both or all HW versions.

I believe the whole point of having software-readable board revision setting resistors would be to tell the firmware which revision-specific parameters and possibly alternate code paths/drivers to use.

[pickle9000]

@ Bud
Do you imagine the HW & Firmware settings Rigol has used to impact on possible ADF4360-7 failure in the future?

Sorry tautech, I do not understand the question, can you explain ?

He's asking if you believe the lifetime of the IC could be affected by operating under these conditions. Can't see it, myself.

Correct Monkeh
Just wondering.....if (as Bud has identified) it's operation OUTSIDE manufacturers recommendations might impact on the IC's MTBF.
Anybody put a IR temp gun on it to see if it's running hot?

@ Tautech, In most cases chips of this sort all come off the same chunk of material. They are then tested and sorted accordingly. In some cases fuses burnt to prevent he device being used as a better / faster variation. Having said that processes improve and the yields of better quality parts go up. It's not unusual to have better chips sold / packaged by the manufacturer of the chip as a lower rated one because there is stock.

Rigol seems to understand the act of pushing these chips and has been doing it for years. The issue is more likely the support components being off. These parts configure the chip (along with the software).

@Muttley S

Hardware revisions are common and software must take this into account. Consider the fact that there are 2 versions of each as is maybe 3 (due to features). Ideally you release one bit of software per series. That makes it easier for the customer to install and for you to deploy.   

[Bud]

Just wondering.....if (as Bud has identified) it's operation OUTSIDE manufacturers recommendations might impact on the IC's MTBF.
Anybody put a IR temp gun on it to see if it's running hot?

I do not think there may be any problem with reduced lifespan. Max electrical specs were not exceeded. But it may shorten the owner's life when he will learn hard way what kind of masterpiece he bought.

[QuadFritz]

Hello-
If one decides to unlock all options on the 1054 (including 100 MHz)- upgrade the firmware before doing so or afterwards?
Thanks!

[sergey]

Just upgraded firmware on my ds2072. So far so good.

I totally confirm AC coupled trigger is fixed now, can't fail it so far with my funcgen.

I can NOT confirm issue with the flash, mine works just fine: being detected just fine after re-insertion.

Didn't have time to test other issues Teneyes reported in the separate thread.

[sergey]

Hello-
If one decides to unlock all options on the 1054 (including 100 MHz)- upgrade the firmware before doing so or afterwards?
Thanks!

It should not matter. Installed options should stay all the same after the upgrade.

[phenol]

I'm wondering whether this pseudolocked PLL condition is stable enough across the operating temperature range of the instrument. I recall some users mentioning that on a cold boot the jitter was there slowly declining to invisible as the thing warmed up.
For some reason, whether insufficient phase margin of the loop filter and/or poor isolation from the ADC (load pull), the phase error seen by the PLL chip is too much for it to assert the Lock mux out pin.

[Lightages]

I am waiting for someone to come up with a user DIY hardware fix for this. I am rather surprised it has not happened yet!

[orin]

I'm wondering whether this pseudolocked PLL condition is stable enough across the operating temperature range of the instrument. I recall some users mentioning that on a cold boot the jitter was there slowly declining to invisible as the thing warmed up.
For some reason, whether insufficient phase margin of the loop filter and/or poor isolation from the ADC (load pull), the phase error seen by the PLL chip is too much for it to assert the Lock mux out pin.

The post-beta pre-final release firmware took up to 6 minutes for the 5us jitter to stop.  It didn't slowly decline for me, the jitter remained the same pk-pk, then suddenly disappeared.  I don't think many outside of Rigol saw this version though.

I've not seen the 5us jitter with the final firmware and am not aware of anyone that has.

[phenol]

so it kind of 'locks' instantly. but the question still remains-how stable is this condition? i am not a proud owner or user of a Rigol instrument, all i have access to is R&S and tek gear, but if i had one, i'd chill the PLL area to 0-5C and see if it gets flappy.

a few words on the vco core current setting...maybe they are trying to squeeze the last dBm of power from the poor sucker so they can clock the adc directly w/o further buffering/amplification

[Bud]

If so they had confused VCO Core Power with Output power, which is a separate setting. Told that 500 times before but let me repeat again - they have no idea what they are doing. But general public in this thread , which should be called consumer blog , not engineering one, seems to feel ok with it. So best of luck to everyone using their "shelf decoration".

[phenol]

If so they had confused VCO Core Power with Output power, which is a separate setting. Told that 500 times before but let me repeat again - they have no idea what they are doing. But general public in this thread , which should be called consumer blog , not engineering one, seems to feel ok with it. So best of luck to everyone using their "shelf decoration".

not sure if there's a mention of it in the PLL datasheet, but there power delivered by the output diff pair could depend on the vco core power, too, provided the emitter current source is configured for 11mA.
The bottom line is that this clock source shall remain in the PLL purgatory, neither dead, nor alive, in a kinderscope coffin.

[MarkL]

Had a chance to do some temperature testing on the PLL and surrounding area with the new firmware on a DS1054Z.

The temperature was not scientifically controlled, but I can say we cooled it down enough to make it frosty, and then heated it up for a couple of minutes with a 100C air pencil.  That should be sufficient for most operating environments.

The one caveat is that we didn't directly heat or cool the loop components because those are on the bottom and required further disassembly.  But heating and cooling were applied long enough so those components experienced a temperature shift.

In short, there was no lapse into crazy instability, at least with this one sample.

Spectrum analyzer shots below: Cold, hot, and both superimposed.  The center frequency shifted because the crystal is nearby and changed temperature, but there was no significant change in the 72kHz and 120kHz peaks, although they did move around a little.  And when hot there was a slightly higher noise/modulation.

While we were at it we also looked at AVdd and Vvco for signs of 72kHz and 120Khz ripple.  There was nothing coming from the power supply, but we did see the 70kHz and 120kHz signals coupled into those pins at very low levels.  AVdd and Vvco were both the same.  Analyzer shot below.

The owner was anxious to start using his scope, so it's back together now.  I couldn't think of anything further that should be done.