That's what I meant exactly by the graphical method.
I still find it unclear why would I take the signal out across the drains resistor as the design shows the output taken across drain pin and ground. what am I missing here? and what is the reason to choose this over that one?
May be, you have heard about the Superposition theorem.
To analyze a circuit with more than one generator, you analyze it for each generator independently.
The other generators, are replaced by its internal impedance.
In the case of the FET amplifier, the VDD supply has ideally an internal resistance of zero ohms for the AC current.
When you make the signal analysis, VDD looks like a short circuit an the RD is connected between Drain and earth.
You probably think, that your only generator is VDD, so, I have to tell you about device models.
For the AC analysis, the FET behaves like an AC generator, that delivers a current proportional to the input signal vgs.
The following pictures show that. I am sorry, that the text is in Spanish.
Fig. 12 shows the amplifier. Fig 13 is the complete graphical analysis, with both the static and dynamic load lines.
Fig 16 shows the small signal model of the JFET and fig. 17 shows the model of the complete amplifier.
As far as I know, the books in archive.org are in the public domain.
You will find, that this is an excellent book in English:
https://ia801601.us.archive.org/16/items/ElectronicDevicesCircuits/MillmanHalkias-ElectronicDevicesCircuits.pdf