As basinstreetdesign said, you still have issues with the capacitor layout. Look, a digital clock is a square wave signal, which means that, if the clock speed is 16MHz, there will be components in that signal very faster than 16MHz, called harmonics. These can go well into the hundreds of MHz. At such high frequencies, a signal will take the path of least inductance, which means a path that circles the least possible area. If a fast signal is forced into a path with a big area, the signal will be either weakened or take another path and will arrive at a different time than other components. The result will be a distorted clock signal, or a non-working clock.
Now look at your capacitors. The clock is using a
Pierce oscillator circuit, that requires that the two capacitors C1 and C2 share the same ground. In your circuit, the least area path from the ground in one capacitor to the other is painted yellow:
That is not good. A better idea would be to flip the Pin 8 capacitor, so both caps end very close together, and near the MCU ground pin 5 (sorry for the horrible graphic):
Now the path for the fast signals is much shorter, and the circuit will probably work better.
Then there are other details, that I think Tim hinted at. Possibly, you should isolate pins 5, 7 and 8 in a single patch on the upper plane, and connect with a single via to the ground plane, near pin 5. Or make a separate section of the ground plane only for the clock area, heavily conected by vias to the upper patch, and then connect the upper patch with only one connection to the MCU ground. Essentially, you don't want any AC signal entering or leaving the clock circuit, and the best way of making sure of that is isolating the whole clock section except for one connection for the DC ground bias. And probably, the whole clock section could be made smaller than what you have now, and with more symmetrical connections to each clock pin. There are very gifted people here who will be able to fill the details better than me.