KM45C512B DRAM protocol

[obiwanjacobi]

I have a couple of KM45C512's and I thought it would be cool to try to interface them to my Z80 project.
(I know I cannot connect them directly - part of this exercise is to make a Z80 compatible memory controller from a CPLD that allows me to use (S)DRAM type chips)

I have found a datasheet (7 pages) that sorta outlines the chip's capabilities, but I have no idea how to talk to it.

Is there a standard protocol for reading and writing I should use or...?

I am a noob when it comes to DRAM chips - I know RAS and CAS but thats about it...

[amyk]

It's generic FPM DRAM. The timings are specified in the datasheet, but for actual diagrams you could look for other datasheets or just search for "FPM DRAM timing diagram" and you'll find plenty of information.

This part is larger than a Z80's address space, otherwise you would be able to connect directly since the Z80 has a built-in refresh counter.

[obiwanjacobi]

Would this be good starting point?
https://www.latticesemi.com/-/media/LatticeSemi/Documents/ReferenceDesigns/EI/FastPageModeSDRAMController-Documentation.ashx?document_id=6166

Because I don't know what to look for or how its called, its hard to know if the information is good/what I need...

[amyk]

Start here... https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Asynchronous_DRAM

This is also good: http://archive.arstechnica.com/paedia/r/ram_guide/ram_guide.part1-4.html