At 14V Vdd, its only got about 8nC of gate charge. Even if the Atmega + the 100R resistor limits the average gate current during transition to around 10mA, its unlikely to be spending over 1us in the linear region, and for sub-10us pulses its good for around 70A. It shouldn't be running hot either unless you've skimped on the copper area - worst case it should be dissipating an average of under a watt due to transition losses, and a couple of hundred mW in I
2R losses during the PWM on period.
However a 2A motor could easily have a stall current of around 30A (see:
Getting a handle on brushed DC motor current @ EDN, and take several ms for the current to decrease to within the MOSFET's DC SOA rating. and the 1ms curve on the SOA diagram shows its only good for 15A at 12V Vds, rising to a peak of 30A as Vds drops to 4V. I suspect its either going to need a *MUCH* beefier MOSFET, active current limiting, or a soft start, ramping up the PWM from zero duty cycle to cure this one.
Edit: while I was typing this the O.P.'s posted a scope trace of the gate waveform that confirms its sub-1us rise and fall. Stiffer gate drive would be nice, as there appears to be some oscillation on the rising edge, but I wouldn't call it essential.
Insert 0.01R (or a 50A rated current probe) between source and ground, and do a one-shot capture of the current waveform for the first 10 PWM cycles from stopped, with the full mechanical load on the motor. I suspect you'll see a grossly excessive current peak.