Measurement of different PCB trace width with R&S ZLNE-3 VNA / JLCPCB

[cgroen]

As my Christmas present to myself this year was a brand new R&S ZNLE-3 VNA and a ZN-Z150 calibrator, I thought it would be nice (finally) to measure the impedance of different trace width from JLCPCB.
According to JLCPCB's "impedance calculator" for their JLC7628 stackup, a trace of 11.55 mil should give 50 Ohms.
I made a small 4 layer 1.6mm thick PCB with 4 different traces on it, 8, 10, 12 and 14 mil wide. Each trace was terminated with a 50.3 Ohm resistor (0402, 1%, using thermal relief on GND). All 4 layers had ground pour on them and lots of VIA's.
The clearance around the tracks where 3 times the width of the tracks.
SMA connectors used was Molex: https://www.molex.com/molex/products/part-detail/rf_coax_connectors/0732511150
Cable used was a Minicircuits SMA cable.

As I have not yet received the calibrator for the VNA, I used what I had laying around (open, short and 50 Ohm) of decent quality (I hope..).

Below is the result from 1 MHz to 3 GHz of the 4 different tracks. Now, I'm no RF expert (at all!), so I might have failed in the measurements/setups, if you spot anything strange, please let me know!
It seems that the orange track (10 mil trace) is the one that is least "bad".
Maybe I have had too high expectations, or even more possible, I did something wrong, but I would have guessed that the return loss would have been better ?

EDIT: Smith chart included also

[cgroen]

Zoomed in on the smith chart:

[thinkfat]

To me it looks like the 10mil trace has the closest match. It has the least wiggles in the logmag graph and also on the smith chart is somewhat straight. However, it is quite obvious from the smith chart that the impedance is mostly inductive capacitive and also quite far from 50 Ohms other than at the very start of the frequency range.

Unfortunately, my RF experience is also quite limited so I don't quite know what this is due to. But it seems really quite odd, the S11 logmag graph should stay below at least -20dB reflected power for most of the range, but instead it rises quickly to be above -10dB. That doesn't look good. I suspect a mistake in your layout somewhere, or in the calibration of the VNA. Could you provide the Gerber files for all 4 layers?

I would, anyway, suggest to drop all the thermal reliefs in the GND pads and make the signal pads for the SMA connectors a lot thinner. Also, put ground vias directly under the connector flanges, not somewhere outside. This all adds inductance.

It would also be quite interesting to see what difference a much wider clearance between the signal trace and the ground fill on the top layer would make and if you were to make another set of boards, have one 10mil trace with SMA connectors on both ends so that you can measure S21 as well.

Putting SMA connectors on both ends would have been the better test setup anyway, IMHO. But I hope someone with more RF experience will take a look as well.

[cgroen]

To me it looks like the 10mil trace has the closest match. It has the least wiggles in the logmag graph and also on the smith chart is somewhat straight. However, it is quite obvious from the smith chart that the impedance is mostly inductive and also quite far from 50 Ohms other than at the very start of the frequency range.

Unfortunately, my RF experience is also quite limited so I don't quite know what this is due to. But it seems really quite odd, the S11 logmag graph should stay below at least -20dB reflected power for most of the range, but instead it rises quickly to be above -10dB. That doesn't look good. I suspect a mistake in your layout somewhere, or in the calibration of the VNA. Could you provide the Gerber files for all 4 layers?

I would, anyway, suggest to drop all the thermal reliefs in the GND pads and make the signal pads for the SMA connectors a lot thinner. Also, put ground vias directly under the connector flanges, not somewhere outside. This all adds inductance.

It would also be quite interesting to see what difference a much wider clearance between the signal trace and the ground fill on the top layer would make and if you were to make another set of boards, have one 10mil trace with SMA connectors on both ends so that you can measure S21 as well.

Putting SMA connectors on both ends would have been the better test setup anyway, IMHO. But I hope someone with more RF experience will take a look as well.

Thanks for input! To be honest, the connectors I used was not what the PCB was laid out for, so it ended up being a compromise...
I have attached the gerbers for the board. I have since changed the layout to the right connector and added a few more things to the board (some experiments with matching circuits etc). This one has also a SMA on one of the "channels", maybe it is better as you write to do this on all of them!

[thinkfat]

I have probably misread the smith chart a bit, the impedance is not inductive, it is capacitive. In that case, I guess the problem is that the ground fills are too close to the signal traces.

To give some reference, I've attached some pictures of a resistive power splitter I made for some experiment. The PCB was done not with a specific impedance controlled stack-up, I just calculated some trace widths for standard 1.6mm FR4 PCB. The PCB was manufactured by JLCPCB, though. As you can see, the reflected power is better than -20dB up to 1GHz (I didn't check higher frequency because the target frequency was below 100MHz anyway). Impedance is close to 50 Ohm across the span, slightly inductive for the most part, turning capacitive towards the end of the range. This is how I expected your smith chart to look like, too.

BTW, what is the frequency/div in your plot? I somehow cannot see that from the screenshots.

[cgroen]

Thanks,
the span is 3 GHz (from 1 MHz to 3 GHz) with 10 divisions, so 300 MHz per division (almost).
I have made some adjustments to the testboard, perhaps I should even make some with more spacing. So far this is it:

(I also made a "cheat sheet" for Smith chart as it is almost half a century ago I looked at that, attached here also)

[m98]

The calculator you used was for a microstrip, not a coplanar waveguide with ground

[thinkfat]

I would be much, much more generous with ground clearance, also around the SMA center pad. You don't need any ground fill adjacent to the signal trace, on the contrary. This is not a CPW or GCPW, you calculated the trace width for microstrip.

PS: quick calculation for a GCPW with 10mil trace and 30mil space gives around 62 Ohms for the JLC7628 stackup.

PPS: I guess your VNA can do TDR as well? That could be quite interesting. What I'm guessing you'd see is a jump where the SMA center pin connects to the trace and another one where the microstrip trace ends in the termination resistor.

[cgroen]

The calculator you used was for a microstrip, not a coplanar waveguide with ground

I would be much, much more generous with ground clearance, also around the SMA center pad. You don't need any ground fill adjacent to the signal trace, on the contrary. This is not a CPW or GCPW, you calculated the trace width for microstrip.

PS: quick calculation for a GCPW with 10mil trace and 30mil space gives around 62 Ohms for the JLC7628 stackup.

PPS: I guess your VNA can do TDR as well? That could be quite interesting. What I'm guessing you'd see is a jump where the SMA center pin connects to the trace and another one where the microstrip trace ends in the termination resistor.

Ahh yes, thanks! I didn't pay enough attention to the type of trace 
If I use Er=4.6, thickness 0.2 mm (as per JLCPCB stackup) a track width of 0.36 mm and a gap (on both sides) of 0.25 mm should arrive at 49.99 Ohm. Does that sound reasonable ?
(thinkfat, I arrive also at 62 Ohm with the numbers used)
Regarding TDR, thats unfortunately an (very expensive!) software option for the VNA....

[thinkfat]

The calculator you used was for a microstrip, not a coplanar waveguide with ground

I would be much, much more generous with ground clearance, also around the SMA center pad. You don't need any ground fill adjacent to the signal trace, on the contrary. This is not a CPW or GCPW, you calculated the trace width for microstrip.

PS: quick calculation for a GCPW with 10mil trace and 30mil space gives around 62 Ohms for the JLC7628 stackup.

PPS: I guess your VNA can do TDR as well? That could be quite interesting. What I'm guessing you'd see is a jump where the SMA center pin connects to the trace and another one where the microstrip trace ends in the termination resistor.

Ahh yes, thanks! I didn't pay enough attention to the type of trace 
If I use Er=4.6, thickness 0.2 mm (as per JLCPCB stackup) a track width of 0.36 mm and a gap (on both sides) of 0.25 mm should arrive at 49.99 Ohm. Does that sound reasonable ?
(thinkfat, I arrive also at 62 Ohm with the numbers used)

Yes, that sounds about right. Maybe you can add that to your test PCB as well. I'm not so familiar with coplanar waveguide structures, I've only read about them. It seems they're a bit fiddly to handle on a PCB because the mode of conduction has a significant electric field "above" the PCB. I've only ever done short microstrip lines at 1 GHz or so, that's where my experience ends. But I've always given plenty of clearance to the top ground fill.

[Leo Bodnar]

I am interested in comparative practicality and accuracy of VNA vs TDR usage for PCB stackup verifications. 
I have used TDR for this but, perhaps, VNA is more modern and portable method?
With TDR it's very easy to see past the launch (SMA or pad) point.  How do you de-embed launch and termination using VNA?
Leo

[cgroen]

.
Yes, that sounds about right. Maybe you can add that to your test PCB as well. I'm not so familiar with coplanar waveguide structures, I've only read about them. It seems they're a bit fiddly to handle on a PCB because the mode of conduction has a significant electric field "above" the PCB. I've only ever done short microstrip lines at 1 GHz or so, that's where my experience ends. But I've always given plenty of clearance to the top ground fill.

I'm adding a few different layouts to the testboard, I will report back here once I get the new boards.

I am interested in comparative practicality and accuracy of VNA vs TDR usage for PCB stackup verifications. 
I have used TDR for this but, perhaps, VNA is more modern and portable method?
With TDR it's very easy to see past the launch (SMA or pad) point.  How do you de-embed launch and termination using VNA?
Leo

I guess you should be able to make a "back to back" PCB with just the connectors (eliminating the trace) and use that. The ZNLE-3 I have has a lot of settings/menus that I have not touched yet, but "de-embedding" etc is mentioned several times on the instrument (and in R&S youtube videos).
Still a lot to learn for me 

[Leo Bodnar]

This is what I have played with - the trace was just an open end trace on PCB panel tooling strip.
I am using Agilent N1020A probe to launch the pulse.

I expect modern VNA to be able to perform inversion solution and output time-domain TDR plot.  Or is it not that simple?

Leo

[cgroen]

This is what I have played with - the trace was just an open end trace on PCB panel tooling strip.
I am using Agilent N1020A probe to launch the pulse.

I expect modern VNA to be able to perform inversion solution and output time-domain TDR plot.  Or is it not that simple?

Leo

Yes, I think they are capable of that, however in the case of my instrument, TDR has an added cost of around €5000 if I remember correctly (wonder if there are any key generators for that  )

[cgroen]

This is what I intend to do next, if any of you guys have more input / things to add, just say so !
I have made the center pad for the SMA connector smaller than recommended by Molex, they just cover the center pin now.
(numbers in paranthises is calculated impedance)

[thinkfat]

This is what I have played with - the trace was just an open end trace on PCB panel tooling strip.
I am using Agilent N1020A probe to launch the pulse.

I expect modern VNA to be able to perform inversion solution and output time-domain TDR plot.  Or is it not that simple?

At least my NanoVNA V2 can do it. I have not much experience with it, though, I've only played around with it.

[thinkfat]

This is what I intend to do next, if any of you guys have more input / things to add, just say so !
I have made the center pad for the SMA connector smaller than recommended by Molex, they just cover the center pin now.
(numbers in paranthises is calculated impedance)

If you'd add at least one actual microstrip transmission line, say, 11mil, with a couple millimeters clearance to the top ground fill, that'd be awesome.

[cgroen]

This is what I intend to do next, if any of you guys have more input / things to add, just say so !
I have made the center pad for the SMA connector smaller than recommended by Molex, they just cover the center pin now.
(numbers in paranthises is calculated impedance)

If you'd add at least one actual microstrip transmission line, say, 11mil, with a couple millimeters clearance to the top ground fill, that'd be awesome.

Absolutely:
According to calculators, this will result in 64 Ohm? The trace needs (with 2 mm space on each side) to be 0.42 mm to be 50.5 Ohm)
But, when looking at the impedance calculator at JLCPCB, a trace of 11.55 mil should give 50 Ohm, so maybe this is a good test.

[gf]

I expect modern VNA to be able to perform inversion solution and output time-domain TDR plot.  Or is it not that simple?

Basically it is an IFFT. For lowpass mode (which gives the impulse response of S11 or S21 in the time domain) the measured frequency points must be evenly spaced, though, from 0...fmax. This may require extrapolation down to DC if the VNA cannot measure so low frequencies. After adding negative frequencies (with conjugate complex values of the positive ones) IFFT is calculated, whose result is a real-valued signal then, in the time domain. Usually also a window function is applied to the frequency domain data before IFFT to avoid ringing/Gibbs artifacts, but OTOH this smooths the resulting impule respose, so it is a compromise. The step response is the integral (or accumulated sum in the discrete world) of the impulse respose then. The impulse/step response of S11 can also be converted to other units, for instance an impedance profile over time (distance) can be plotted.

A 0...3GHz sweep leads to a time resolution of 6GSa/s, but the smeared pulse width (or rise time) is rather a couple of samples, depending on the selected window function. If a better resolution than a few centimeters is needed, then 3GHz is not sufficient, but a higher frequency range needs to be swept.

At least my NanoVNA V2 can do it. I have not much experience with it, though, I've only played around with it.

It can. Unfortunately it renounces 50% of the possible resolution in lowpass mode (FFT size too snall), and the extralolation is IMO not implemented correctly; fortunately the latter seems to have not too much effect on the result. If the pulse/step starts partly outside the screen, then adding EDELAY of say -1ns helps I order to shift the pulse horizontally.

[nctnico]

If you want to be sure about PCB trace geometry, use a field solver (like Sonnet Lite). PCB trace impedance calculators are usually wrong; especially with trace impedances other than 50 Ohm.

[thinkfat]

If you want to be sure about PCB trace geometry, use a field solver (like Sonnet Lite). PCB trace impedance calculators are usually wrong; especially with trace impedances other than 50 Ohm.

Theoretically. But I don't think JLCPCBs process is well enough controlled to model the PCBs for a field solver with better precision than a beer-soaked-coaster calculation would yield.

[nctnico]

If you want to be sure about PCB trace geometry, use a field solver (like Sonnet Lite). PCB trace impedance calculators are usually wrong; especially with trace impedances other than 50 Ohm.

Theoretically. But I don't think JLCPCBs process is well enough controlled to model the PCBs for a field solver with better precision than a beer-soaked-coaster calculation would yield.

That goes for any PCB manufacturer. But you can mitigate that by choosing the stackup in a way that the trace width is large compared to the etching tolerances. That way you can achieve very accurate results. But that is not really my point; the online calculators just aren't good enough.

[cgroen]

According to JLCPCB, a 50 Ohm trace should be 11.55 mil wide. If I punch the numbers into a calculator, this should give 63 Ohm (at Er=4.6).
Something is clearly not right ?!

So far, my next testboard looks like this (ideas more than welcome, I will be ordering in a couple of days)

[nctnico]

Again: Use Sonnet to check your trace geometries!

[2N3055]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

0.29 mm trace/spacing on 1.5 mm gives 49,9 Ohm

That is in AppCAD.