Open-source software for Verilog synthesis

[tim]

Oh, and by the way, yes, TimberWolf can be a pain to compile.  I'd rewrite the whole installation process if the thing weren't such a bloated beast.  If you have specific problems with the TimberWolf compile, just tell me what they are and I can probably get you through the compile stage.

[Unixon]

Thanks a lot, Clifford. I've been away from this forum for quite a long time due to total mess at day job and other activities usually occurring at the end of year. Currently I'm working on few microcontroller projects and specific tools for managing gerbers and EDA files, but I think I still can advance in small steps with respect to declared plans.

Tim, thank you for support, I will definitely need your help in dealing with these tools. I will see what is exactly wrong with that build as soon as I get near my workstation, probably next week.

[Unixon]

Quickly browsed through Clifford's papers about Yosys. Brilliant. This looks like something I've been missing so much while trying to wrap my head around Yosys workflow.