Nesys 2 and user constraints file

[naimis]

I recently bought Digilent's Nexsys 2 dev board and their associated textbooks to try and teach myself how to program FPGAs in Verilog.  It didn't take long for me to run into trouble.

The board I picked up is based on the XC3S1200E in the FG320 package.  The publisher of the book and/or Digilent provide a UCF for the Nexsys 2 board. This was probably for a different package, however the silk screen labels on the board match up at least.  That said, "it still doesn't work".

1) I get a bunch of errors about nets not being found. These are nets defined in the UCF tied to functions that aren't in use in this project. Understandable, somewhat, but why is this an error? It's bizarre to me that I can go through the synthesis, implementation and bit file generation without a UCF to tie any pins to nets at all with NO errors, but if I have unconnected/unused nets in the UCF that's an error.  Still, this is easy to resolve.

2) The difficult part is this: the pins that the LEDs are labeled as being connected to are invalid. LD(7:4) are supposedly tied to R4, F4, P15, and E17 respectively. These, however, are user input pins, not user I/O pins.  The PlanAhead program won't let me tie the ports (LD) to the sites.  What's more, four of the switches appear to be tied to global clock pins rather than user input or user I/O pins. Probably not unheard of, and it certainly appears to be allowed, but a little strange in my eyes.

I'm sure I should be contacting Digilent directly about this (and probably will be soon), but I figured I'd throw this out here in case someone else has already run across this... Just looked at the Spartan 3E data sheet and site R4 is I/O in the 500E but in this 1200E, it's an input.  I sure hope Digilent's engineers didn't get lazy and tie LEDs to input pins.

... Looking forward to Dave's latest round of FPGA videos

[naimis]

Aside from the obvious answer for the UCF errors (removing extraneous entries), there's also an "Allow Unmatched LOC Constraints" option in the translate process properties. The option turns the errors into warnings though, so the only way to silence the tool chain is to use or delete the nets (apparently).

[mrflibble]

I have a nexys2 with XC3S1200E as well. See attachment for the ucf.

[mrflibble]

... there's also an "Allow Unmatched LOC Constraints" option in the translate process properties.

That's not the best of ideas, unless you know exactly why you are doing it.

[naimis]

I have a nexys2 with XC3S1200E as well. See attachment for the ucf.

THANK YOU. Working as intended. Where did you get that UCF? The one available for download from Digilent for the 1200K was basically the same as the 500K.

The silkscreen is wrong on the board, then, and their provided UCF file is as well... I'm glad to see they didn't *completely* botch the job.

[mrflibble]

I have a nexys2 with XC3S1200E as well. See attachment for the ucf.

THANK YOU. Working as intended. Where did you get that UCF? The one available for download from Digilent for the 1200K was basically the same as the 500K.

The silkscreen is wrong on the board, then, and their provided UCF file is as well... I'm glad to see they didn't *completely* botch the job.

Pffff, don't even remember, so long ago. Either I edited it based on schematics/silkscreen/pixie informants, or I googled it and got lucky. Looking at the lack of pin name + type, I got it elsewhere because those UCF entries are not my style.

And yes as you noticed, the silkscreen is WRONG! and the schematic is for 500K only... Luckily those 4 leds are the only UCF related fuckup, the rest is all correct AFAIK. Consistent documentation & support files are not Digilent's main strengths, but I still like their hardware.