DIY sine generator SG-642

[Liv]

Features:

• frequency range: 0.1 Hz - 50 kHz
• frequency resolution: 0.001 Hz
• phase range: ±360°
• phase resolution: 0.1°
• output amplitude: 0 - 10 V
• amplitude step: 0.01 V
• attenuator: 0 dB, -20 dB, -40 dB
• output impedance: 50 Ohm
• meander mode
• 10 presets
• digital calibration (frequency, amplitude)
• interface: USB (optocoupled)
• case type: Z-4A (160 x 140 x 60 mm)

Probably, this generator is stupid project, because all of its features provides a sound card of the computer.

Pulse generator PG-872

[Yansi]

Thats really nice! 

Mmm and some I2S DAC there too driven by an AVR

[Liv]

I2S emulation and DDS implementation with interrupt latency align and interpolation to 16-bit resolution -  this is the most interesting in this project.

Code: [Select]

                                ;4      address store
DDS:    lds     ZL,TCNT1L ;2      TCNT1L = 5..8
        ldi     ZH,high(JmpTab) ;1
        ijmp                    ;2

.org (PC + 0x100) & 0xFF00   ;align to page

JmpTab: nop                     ;       dummy
        nop                     ;       dummy
        nop                     ;       dummy
        nop                     ;       dummy
        nop                     ;       dummy
        nop                     ;0/1    TCNT1L = 5
        nop                     ;0/1    TCNT1L = 6
        nop                     ;0/1    TCNT1L = 7
                                ;       TCNT1L = 8
in tsreg,SREG ;10/13  save status register

out SPDR,SinH ;1 ---> load DAC L high byte

add APhaseK,AFreqK ;1      Phase(0..33) = Phase(0..33) + Freq(0..31)
adc APhaseL,AFreqL ;1
adc APhaseM,AFreqM  ;1
adc APhaseN,AFreqN  ;1
adc APhaseP,zero    ;1

mov ZL,APhaseN ;1      ZL = wa (word address)
mov r0,APhaseM ;1      r0 = dx
sbrc APhaseP,0 ;2/1    if(Phase.24 == 0)
com ZL ;0/1    wa = !wa
sbrc APhaseP,0 ;2/1    if(Phase.24 == 0)
com r0 ;0/1    dx = !dx

ldi ZH,high(LUT) ;1      ZH = table base (low(LUT) = 0)
add ZL,ZL ;1      offset * 2 (word offset)
adc ZH,zero         ;1

ldi SinH,44         ;1
sts OCR1BL,SinH     ;2

out SPDR,SinL ;19 ---> load DAC L low byte

ld SinL,Z+ ;2      SinL = lo sin[x]
ld SinH,Z+ ;2      SinH = hi sin[x]
ld r1,Z ;2      r1 = lo sin[x + 1]
sub r1,SinL ;1      r1 = dA
mul r1,r0 ;2      r1,r0 = dA * dx
rol r0 ;1      C = 1 if r0.7 == 1
adc SinL,r1 ;1      SinH:SinL = sin[x] + round(r1:r0 / 256)
adc SinH,zero ;1      SinH:SinL = A

sbrs APhaseP,1       ;2/1
rjmp ph_cd1 ;0/2    jump if Phase.25 == 0

ph_ab1: com SinL ;1/0    SIN > 0, data line has NOT gate,
com SinH ;1/0    SinH:SinL = !SinH:SinL
rjmp ph_ad1          ;2/0

ph_cd1: sec                     ;0/1
sbc SinL,zero       ;0/1    SIN < 0, data line has NOT gate,
sbc SinH,zero ;0/1    SinH:SinL = SinH:SinL - 1

ph_ad1: out SPDR,SinH ;38 ---> load DAC R high byte

add BPhaseK,BFreqK ;1      Phase(0..33) = Phase(0..33) + Freq(0..31)
adc BPhaseL,BFreqL ;1
adc BPhaseM,BFreqM  ;1
adc BPhaseN,BFreqN  ;1
adc BPhaseP,zero    ;1     

mov ZL,BPhaseN ;1      ZL = wa (word address)
mov r0,BPhaseM ;1      r0 = dx
sbrc BPhaseP,0 ;2/1    if(Phase.24 == 0)
com ZL ;0/1    wa = !wa
sbrc BPhaseP,0 ;2/1    if(Phase.24 == 0)
com r0 ;0/1    dx = !dx

ldi ZH,high(LUT) ;1      ZH = table base (low(LUT) = 0)
add ZL,ZL ;1      offset * 2 (word offset)
adc ZH,zero         ;1     

ldi SinH,81         ;1
sts OCR1BL,SinH     ;2

out SPDR,SinL ;56 ---> load DAC R low byte

ld SinL,Z+ ;2      SinL = lo sin[x]
ld SinH,Z+ ;2      SinH = hi sin[x]
ld r1,Z ;2      r1 = lo sin[x + 1]
sub r1,SinL ;1      r1 = dA
mul r1,r0 ;2      r1,r0 = dA * dx
rol r0 ;1      C = 1 if r0.7 == 1
adc SinL,r1 ;1      SinH:SinL = sin[x] + round(r1:r0 / 256)
adc SinH,zero ;1      SinH:SinL = A

sbrs BPhaseP,1 ;2/1
rjmp ph_cd2 ;0/2    jump if Phase.25 == 0

ph_ab2: com SinL ;1/0    SIN > 0, data line has NOT gate,
com SinH ;1/0    SinH:SinL = !SinH:SinL
rjmp ph_ad2          ;2/0

ph_cd2: sec                     ;0/1
sbc SinL,zero ;0/1    SIN < 0, data line has NOT gate,
sbc SinH,zero ;0/1    SinH:SinL = SinH:SinL - 1

ph_ad2: out SREG,tsreg ;1      restore status register
reti                    ;4
                                ;89/92  total


[dom0]

Probably, this generator is stupid project, because all of its features provides a sound card of the computer.

Except that most sound cards have a higher SFDR (and thus lower THD) than the TDA1543 (~75 dB SFDR to harmonics, other spurious responses should mainly depend on supply and PSRR)

[Yansi]

Forget that TDA1543 is almost vintage, it is still a masterpiece.

How much time have you spent making this?


//small curious question, what is the functionality of DETx signals?

[dom0]

Quick glance: VT5 peak detector, R64+R65+R61, C73 filter network. So it's probably for amplitude servoing as it goes to the main controllers ADC.

[Yansi]

Possibly, I only don't understand why the base of VT5 goes where it goes, not directly on the output then.. ?

[dom0]

The trick here is that he uses a complementary buffer stage (circuit is described en detail in Jim Williams app note no. 47 (linear technology), AN47 page 46). This means that VT8 + VT14 amplify* the positive half of the signal and VT9 and VT17 the negative half. So at the emitter of VT8 you'll only ever get positive swing, and very much so at the base of emitter follower VT5.

* only current amplification. Usual voltage drops apply ; are compensated by the feedback loop.

[Liv]

higher SFDR

I wanted to make a sine generator based on a modern 24-bit DAC. But the generator SG-642 is enough for me (audio measurements do not mean).

Forget that TDA1543 is almost vintage, it is still a masterpiece.

This DAC is freely available today.

How much time have you spent making this?

I had a few versions of such a generator (for example, SG-420M), so spent a few years.

//small curious question, what is the functionality of DETx signals?

This is detected output level signal. Used for filter frequency responce calibration.

[dannyf]

Interesting project.

I2S emulation and DDS implementation with interrupt latency align and interpolation to 16-bit resolution -  this is the most interesting in this project.

You can do that in C by outputing the msb/msw of the phase accumulator to the port/ports.

[Liv]

No, in C I'll never get this performance. Given the dedicated registers, the difference will be many times.

[dannyf]

Given the dedicated registers, the difference will be many times.

In C, you can read/write those "dedicated registers" just as well.

[Liv]

No, in C I can't allocate 22 registers for my task. This is a good example what can be done in ASM, but can not do in C.

[pickle9000]

That is very nice work, great stuff for the resume. 

[dannyf]

I played around on a PIC16F886 (non-buffered spi send). I can complete the transmission of two channels (32 bit data in total) in 150us (=6.3Khz), on a 4Mhz oscillator (1MIPS). All done in C.

On a mcu with a buffered spi, I can double the speed. So it is entirely doable in C for audio frequency output.

[Liv]

I have a sampling frequency of 206 kHz, for this time is calculated 2-channel DDS with interpolation and transferred to 2-channel 16-bit DAC in I2S. When the CPU speed of 20 MHz (20 MIPS).

[Chris56000]

Hi!

I only recently joined the EEV Blog Forum and I came across your Projects whilst looking for schematics for lab supplies!

Member Liv. I'd like to express my personal thanks to you for providing details of this suite of economical easy-to-build instruments that any hobbyist or electronics student can build from your plans, and please don't feel anything you post details of has been a waste of time or stupid!

You've put a lot of work into each of these and I congratulate you for the time and effort you've taken!

Chris Williams

[Liv]

Thank you very much for your feedback!

[Yansi]

Have you thought of using a CPLD+SRAM and a multiplying DAC instead? Could made possibly a nice arbitrary wave gen up to few MHz (tens of MSps at the DAC) for very cheap with quite interesting specs though.

[Liv]

Yes, I had plans to make AWG based on Altera Cyclone and AD7744. Even designed an analog circuit board. But then the work was abandoned.

[Chris56000]

Hi!

I have now found out Liv's original display is now unobtainable, as are the equivalent replacement ment types!

I have contacted Liv by PM to see if he still has his native PCAD design files, so I can use them as a starting–point to make a replacement front PCB that will drive a cheap standard 128 × 64 Graphic LCD Module of the ST7920 type, with an MCP32017 or PCF8574 to interface Liv's I²C interface to the parallel LCD module, and await his reply if he's still available!

Chris Williams

[Liv]

PCAD files can be found on this page: http://www.leoniv.diod.club/projects/measuring/sg-642/sg-642.html