filtering a output of xor-ed signal

[tarunkumartars]

HELLO,
I have two signal yellow and green which i'm doing an xor operation with both and now i get blue signal as an output but the problem is it has a spikes as you can see in every half period. could someone help me in removing that or any ideas?

P.S i'm just playing with gates and i wanted to see if the online simulation and theoretical results matches with my hardware setup which aren't matching because of the transition spike. And here BLUE signal is my final output .

thank you

[rs20]

This is just a race condition / glitch. 0 XOR 0 = 0 and 1 XOR 1 = 0, but no two events are ever truly simultaneous in real life, so in a transition from 0 XOR 0 to 1 XOR 1, you're inevitably going to go via 1 XOR 0 or 0 XOR 1, which both equal 1. So, the circuit may briefly output a transient spike. That's the origin of the spikes in your signal; two of your inputs "simultaneously" rise, but nothing is truly simultaneous. As noted in the linked articles, these sorts of glitches can occur in real circuits, but in a proper synchronized/latched circuit, it's never an actual problem. The latches ignore the glitches, real designs don't make any effort to "filter" them out using RC circuits or anything like that.

P.S i'm just playing with gates and i wanted to see if the online simulation and theoretical results matches with my hardware setup which aren't matching because of the transition spike.

I gotta say, if you're only concern is that the spikes cause a mismatch between simulation and theory, then:

• Just disregard the spikes using your brain
• Or use a better simulator that will show you the spikes which your circuit should and will make
• Or run your circuit at 1kHz instead of 1MHz, which will make the glitches appear a thousand times thinner and less noticeable.
• Or, instead of using two signals with different frequencies as your input (1 MHz and 500 kHz), use two 500 kHz signals that are in quadrature. No simultaneous transitions --> no glitches.
• Or add synchronous latches to your circuit
• Or, if you really really insist, add an RC circuit with a cutoff frequency of about 5 MHz to the output. Calculators for RC circuits can be found online.

On a side note, those signals look terrible. Are you connecting the ground clips of your oscilloscope probes to a reasonable ground?

[tarunkumartars]

thanks for the detailed reply. would try to filter out the signal above 5mhz .yeah the ground is not so good as i used transistors to make the whole xor on a brown board

[RoGeorge]

could someone help me in removing that or any ideas?

You may want to search about "asynchronous vs synchronous digital design".

What you have there is an asynchronous design.  Any CLC (Combinational Logic Circuit) is asynchronous, and might generates spikes.  To avoid that, turn the CLC into a synchronous design, by adding latches (simple D type flip-flops will do it) and a common clock that drives the whole logic.