PCB layout and stackup for space application

[Luca_Daidone]

I've been tasked with the design of a PCB for a CubeSat project in my university and I'm trying to figure out exactly how the layout and stackup of my board should be done.

The board I have to design is for power distribution, this means that on the board there will be mainly DC DC converters and an IC for battery management. I forsee that 4 layers will be needed.

For the design I must take into account the ECSS guidelines (European Cooperation for Space Standardization) and I've been studying the relevant standard (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwimyPfI88r1AhXRR_EDHbduCWcQFnoECAYQAQ&url=https%3A%2F%2Fescies.org%2Fdownload%2FwebDocumentFile%3Fid%3D62466&usg=AOvVaw3rpnrTAX8y84w2E_JSMVfm&cshid=1643045117480261). I'm extremely confused by few of the rules listed on the document, for example:

7.4.3 point e) Tracks should not be routed on external layers.
13.9.3.3 point b) In case critical tracks are routed on external layers, they shall not be routed under components.
I guess this is to improve EMI and radiations immunity but it means that the stackup of the board can't be like the "standard" stackup (signals on external layers and internal GND/power planes) but must be something like GND on top and bottom layers and signals&power in the inner layers.

I understand the upsides of this stackup (two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a faraday cage, signals and reference plane very close to each other etc.) however I can't really imagine to place a via for each signal coming from every smd pad: it looks like a routing and signal integrity nightmare to me.

For example the feedback loop of a DC/DC converter must be routed as short as possible and going from the top layer to the middle one and coming back to the top layer doesn't sound very wise to me.

Also so many vias means many via stubs acting like antennas. Probably an hybrid stackup would be better (signals and ground on top layer) but then why not going with the "classic" stackup.

7.8.2.2 point a)Solder mask shall not be used.
7.6 point a)Copper planes should have additional openings in a grid format.
Since outgassing it's a big issue in space applications, they forbid the use of soldermask and suggest to apply a layer of conformal coating after the assembly. Also they suggest hatched polygons in order to allow humidity to get out of the board easily.

These points puzzle me a lot since all the boards we're buying from the industries, rated for space, come with solder mask, no conformal coating and full polygons. Also I'll be probably soldering the firs prototype and I'm afraid that by having no solder mask the tin will flow away from the smd pads.

Do you think that a stack up with signals only on internal layer is feasible? Are via stubs and feedback loop length a reasonable concern at the frequencies at which the DC/DCs are working? Do you have experience with such design? Should I remove the solder mask completely or maybe only on few spots?

These guidelines don't really make sense to me but I can't play by my own rules without justifying them first to the team.
Thank you!
Luca.

[Siwastaja]

If you use SMD components, the usual layout just places the components as close together as possible, forming tiny, short traces between them. What you should do? Add vias to go to mid layer, them come back with another via? That's more track on the top layer compared to if you did it fully on top alone.

Maybe this is some leftover from through hole days, when you could pick any layer, and layouts were sparse?

If nothing else, components are susceptible to EMI anyway. This is why a top/bottom layer ground fills are not silver bullets. Also exposed vias - assuming you don't use buried vias, which suck. What really works is an actual shield, which can fully enclose the board layout and components. You can buy those metal cans which are soldered on the board.

[Luca_Daidone]

Thanks for the insight! I totally agree with you, however I've asked the same question to different people and I've gotten different answers
A guy who designs PCB for space applications told me:  "A stackup with signals only on the inner layers is not only possible, but may be preferred. That is our standard approach. On most boards, the only traces on the top layer are for short traces to allow connections from pads/pins to vias going down to internal layers."
So I'm more confused than before

[Siwastaja]

OK, that reply confirms my suspicions.

It's just non-technical double speak.

They say "no traces", yet they mean "no long traces". A huge difference, isn't it!

This also basically confirms the standard is wrong, it cannot be followed, because even those who claim to follow it, in the next sentence admit they follow a different rule: accepting certain length of traces when going to via.

Where you set the threshold of "long trace", makes it more inaccurate art, than exact science. Maybe 10mm? 20mm? 100mm?

And why adding two vias makes it good, even if the track length on top layer increases due to that?

It's hilarious in how far people go to support their fallacies. So they can break the rules by making a short trace, but only if it goes to the via, comes back from another via, to another short trace; the vias are acting as symbols of "I did something to try to follow the impossible rule, which I still didn't follow, but hey, there are vias!" In reality, they just make the rule breach bigger, because the vias add more copper area to the track, compared how short it could be if you did not jump into the mid layer.

The key of survival in such absurdly regulated field is to sense the atmosphere, trying to socially figure out what are the socially set, non-written actual rules, how strong their enforcement is, i.e., do you get in trouble if you follow the actual rules, or in case that is impossible and no one are following the rules, at least do the Right Thing. Finally, try your best to mitigate the negative effects of said rules (official and made-up).

This is exactly why I hate such regulated fields. With some good regulation, comes also broken regulation, and with good social high-status job, come also sick social games. Navigating in that minefield and get out products that allow you to sleep at night requires experience. I would suck at that job, I would just concentrate on making things work and be safe and reliable, based on the physical reality.

In through hole design, this insanity does not exist: the length of the track is the same regardless of being on outer or inner layer, and no extra copper needs to be added to hop between layers, so such rule does not hurt and might help with EMI, a bit. Simplistic rule of thumb, but not super-harmful.

With modern high-density SMD, it totally blows everything up and forces to do inferior design, EMI-wise and otherwise.

[Robotec]

Well ,  going to  give my limited insight in this field (I worked for around 3 months in an internship in Space company doing schematic stuff), thing is that I was interested in how the PCB layout was done as well and this was what I gathered:

1-The routing had to be symmetrical(this was a MUST): example: TOP-GND-POWER-SIGNAL-GND-GND-SIGNAL-POWER-GND-BOTTOM.(16 layer boards is normal there)

2-Only space grade components, thing is that a LOT of them were TH this is were your no traces in first layer comes from, very few modern IC´s are space grade so for example, when designing a Linear regulator we did it from voltage reference, opamp, transistor etc no such thing as a nice 78XX.

3-ancient IC were used, I mean a lot of 74HCXX were used as well. As before, all space grade(EXPENSIVE as hell, 1 resistor around 1$).


don't know if the requisites for CUBESAT are lower but this is I why didn't want to design for space, it was like designing something out of the sixties.

So in short you are gonna have to design something analogic or a simple dc/dc,  probably controlled by something like a 8051(for example) monitoring the power supply and state of the battery, with parallel or low baud rate.

[tszaboo]

For example the feedback loop of a DC/DC converter must be routed as short as possible and going from the top layer to the middle one and coming back to the top layer doesn't sound very wise to me.

The vias don't add significant length to the feedback path. It's just going from L1 to L2 then it's like 0.6mm added length by two vias.

Since outgassing it's a big issue in space applications, they forbid the use of soldermask and suggest to apply a layer of conformal coating after the assembly. Also they suggest hatched polygons in order to allow humidity to get out of the board easily.

The cubesat PCB that I saw had no soldermask.

These points puzzle me a lot since all the boards we're buying from the industries, rated for space, come with solder mask, no conformal coating and full polygons. Also I'll be probably soldering the firs prototype and I'm afraid that by having no solder mask the tin will flow away from the smd pads.

Space rating and rating for vacuum is likely to be different. They were using Lenovo X200 for example which are space rated on the ISS, but they are likely not going to work in vacuum. You probably have to fix any soldering issues by hand after the automated assembly (if there is even automated assembly). This is normal since you are making only 1 device.

Other student teams have documented their PCBs so I would look up what they did.

[amosborne]

I work in space.

I recommend you figure out your board house and work with them to define materials, manufacturing capabilities, applicable reliability standards, etc. Soldermask can be done, you will need conformal coat.

Standards are standards, not regulations. They are to serve as a guide, not a bible. For layer stack up, consider reading Henry Ott’s book on electromagnetic compatibility. 4 layers will not give great performance, but that depends entirely on the content of your PCB and you EMI requirements.

High speed routing works better on internal layers as a microstrip (rather than stripline on top layer). Electric field does not spread as much which allows you to pack traces closer together and not coupled into other stuff. Yes ground planes also provide “shielding”.

Sometimes rules for space aren’t obvious as to their rationale. Traces under integrated circuit might not be recommended partly because it’s not visible when the component installed, making it not able to be inspected.

[moffy]

I worked with military and some space in the early 80's and found that the approved components/technology was around 10 years behind commercial because of the approvals process. Then a decade or so later the military, at least US, went with commercial devices because the only difference was the level of testing, they both came off the same production lines. Caps were 50% derated, and power semis were 60% derated, just our design rules.  Space, outgassing was the big issue, though fighters at 60,000 ft face almost the same issues. Our boards had a solder mask and vacuum applied conformal coating, almost impossible to repair boards after it was applied, you couldn't solder through it. Don't think electrolytics of any sort were allowed because of the outgassing issues. Boards tended to be thicker than normal for mechanical rigidity, and vibration resistance. No tall, thin components because of vibration. Any large component, we had 1uf Teflon caps, tubular, for the accelerometers would have to be tied down with cable ties to the board. No glues allowed, again for outgassing reasons, though I think there were some allowed potting mixes.
Long time ago, things have probably changed a lot.

[m98]

Few bits from my experience:
What orbit are you aiming at, and what is your target mission lifetime? Your typical LEO cubesat mission doesn't need to even start worrying about any rad-hard or even rad-tolerant components.
Even commercial nanosatellite subsystems mostly contain AEC grade 1 components. However, where sensible, you have to apply a heavy de-rating to most components. So a MOSFET with a Vds of 80 V should for example only be used to switch up to 16 V. Things like integrated, synchronous DCDC converter ICs therefore can't be used. Also, always use flexible terminated MLCCs.
As you are designing a PCDU, don't forget latch-up protection.

Go 6 layer instead of 4. Saves you all kinds of EMI headaches, as you can't easily move signals between layers on a 4-layer stack up without impedance discontinuities. And if you want to learn some EMI best practice, Robert Feranec has some great videos.

Solder mask should usually be fine, but some silkscreen prints are rumored to outgas, so better just leave that away. FR4 is usually fine, but make sure the laminate is from a reputable supplier that provides outgassing data. Isola IS400 is good. No special rules for copper planes, hatched copper planes are not necessary for modern rigid PCBs and can create even more EMI headaches. Also, no HDI techniques like blind or burried vias unless absolutely necessary.

Before you conformally coat the assembled PCB, it needs to be thoroughly cleaned of every last bit of flux residue and you need to bake it out according to IPC 1601, we usually do 120 °C for 6 hours.  There are some low-outgassing conformal coatings for brush-application, but beware of silicone, most silicones outgas like crazy if not specially formulated for the application. Alternatively, you could let your assembly be coated in Parylene by an external supplier, that's basically the big-space gold standard, but it's also unnecessarily expensive.