OK then, lets dig in to the mess with the 7474 logic ICs. Prior to this I had no specific idea how this circuit works, so I'm figuring it out with you right here.
The 7474 is a dual D-type flip-flop, each half works independently but they share power and ground. The general idea of the trigger circuit is that when it sees a trigger pulse coming from U601, it turns on the beam (UNBLK PULSE to R521) and starts the timebase generator sweep. It then ignores any additional trigger pulses until the timebase sweep is done, then the circuit resets and waits for another trigger.
Looking at this circuit, we can start with the 1/2 of the 7474 that gets the trigger signal. By your scope shots we can see that power (14) and ground (7) are good, so we only need to worry about pins 1 to 6. Since it is TTL logic, the signal should be mostly either around 0 volts or 5 volts--LO and HI. Pins 1,2,4 and 5 are HI, pin 6 is LO and pin 3 is the only one that moves--it is seeing the trigger signal from U601. We then have to look at the function table to see what that all means and what state the flip-flop is in. Pins 5 and 6 are complementary outputs Q and Q
not, which means they will generally be the opposite of one another, with the transient exception shown.
Pins 1,2 and 4 are inputs CL(ea)R, D and PR(eset), so all three being HI correspond to the 4th line in the function table. If the D line were to revert to low, you would expect the outputs to flip on the next trigger. However, by the wiring diagram, you can see that D is connected right to +5V, so it will never be low. As you can see by the function table, the only other way to get the flip-flop to transition would be for the CLR to go LO while the PR stays or becomes high. Then the CLR would have to revert to HI and the flip-flop would be 'armed' and ready to transition back to the fourth state when the CLK transitions from LO to HI.
It is hard to say where the problem so far. It looks like CL (pin 1) is pulled low by pin 8, which is the Q output of the second half--we need to call these CL1 and Q2 now--so now we have to look at the second D-flip-flop. Pins 8,9,10,11 and 12 are all high, pin 13 is low. So the only way both outputs can be high is line 3, which requires PR2 and CLR2 to both be low--which they aren't. So something is wrong here. I had a closer look at the scope shots and I now see that Q2 pin 5 is not all the way high--3.40 volts indicates a problem or struggle with excessive source current. Q2
not is also not all the way at 5 volts, so it may be trying to go low but something is exceeding its sink current limit. Or maybe the 7474 is bad--that would be too obvious!
Here are some things to try next:
Use your scope and check all the pins of Q601, Q602, Q603, Q604 and Q605. I'm not sure how they are marked on the board, so photos may help. Then check C618 and C629 to make sure they aren't shorted to ground. Then fidn a way to disconnect the wires that go to UNBLK PULSE and ALT (at the top of the diagram) and then recheck al the pins of U603 to see if anything changes.