Well it does really. It’s no secret what they did.
State of the art 8-way superscalar processors without running into a million patents are billion dollar endeavours, M1 does nothing to make this easier for ARM/RISC-V implementations from other companies ... it doesn't even help create a market for them, unlike how things happened on PCs. Boring.
There was a rush of superscalar Out-of-Order processors in the mid 90s.
The Pentium Pro did 3-wide decode (generating up to 6 uOps total), 5 wide execution (in 6 units) in 1995.
The DEC Alpha 21264 had 4-wide decode, 6-wide execute in 1996.
Patents for those, and others, have expired by now.
Decoding 8-wide instead of 4-wide on a simple fixed length 32 bit opcode instruction set such as Alpha or arm64 is just a parameter -- literally changing a "4" to an "8" in an RTL generator. Exactly the same (expired) patents will cover it.
The hard part about it -- and more to the point having 600 reorder buffer entries as M1 does (192 or 224 are popular numbers on modern x86) -- is something I haven't seen *anyone* mention in any thread on any forum or media report. It's not that hard to change the parameters to do that, if you have enough transistors available on a die (i.e. a small process). The hard part is that most code has, on average, a branch instruction every five or six instructions. If you are going to have 600 instructions in flight at the same time then you have to be reasonably sure they are the RIGHT 600 instructions.
That means you have to accurately predict up to about 100 conditional branches in sequence. If you get any one of them wrong then you have to throw away all the work you did on following instructions, wasting both time and energy.
You can build as wide and deep a machine as you want -- it's straightforward -- but if you can't predict the branches accurately then it's totally wasted.
Apple must have done something quite amazing and absolutely unpublicized about branch prediction.
Branch prediction was also the most secret thing about the Pentium Pro back in 1995 -- and Pentium MMX got the same branch prediction technology and was what made it a big jump over earlier Pentiums (not the MMX).
These days, microcontroller cores such as the SiFive FE310 (and probably ARM M3/M4, certainly M7) have the same branch prediction technology the Pentium Pro pioneered -- not because they're out of order, but just to eliminate pipeline bubbles most of the time.
Building an 8-wide decoder for x86 is exponentially harder. The instruction lengths from 1 to 15 bytes mean those instructions could occupy anywhere from 8 bytes to 120 bytes. And you have no idea where later instructions start until you've already done most of the decode on earlier instructions. It's just intractable on cold code. On hot code you can add marker bits for the start of each instruction in the L1 cache, and have a uOp cache, and so forth. But that's all extra complexity and transistors and energy use that arm64 or RISC-V don't need.