EEVblog Electronics Community Forum
General => Jobs => Topic started by: aventuri on February 28, 2018, 09:06:34 am
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hello,
the title pretty says it all.. we need to "grow" a digital audio link from TDM/8 to TDM/16 using a small FPGA as "man in the middle".
an ASRC has to be implemented too, because sample rate and clockfor the added link could be different/async.
we are looking for a consultant doing the verilog design in a few months. it's a remote task, of course; we shall provide the HW for the development and test.
for those interested, i can provide a small RFP for further evaluation and quotation. feel free to ask me on PM for clarification
thanx for attention
andrea
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Does it really need to be Verilog? If you drop that requirement you'll have more luck finding someone because VHDL is more often used in Europe than Verilog. I have quite a bit of experience with managing audio streams using FPGAs and VHDL.
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good question. we too are European but Verilog is indeed a pre-requisite because we want to go with an ICE40 UP5K and then the route of the open source toolchain Yosys / Arachne-pnr / Icestorm (or using as fallback IceCube2 - Radiant looks a bit "early"..) to get the most control about this development.
it's not a high performance solution involved, so thos path should be feasible IMHO, always open anyway to hear about "issues".
OTOH Vhdl and Verilog are not that far each other (if you stick with the "more standard" language constructs and HW principle to be more "portable" across vendor toolchain), maybe i can send you the RFP anyway, for you to give me a more focused feedback. if you already have working experience on digital audio HDL design, you are quite qualified in my point of view. for the "syntax" we can always find a workaround!