I have just completed a PCB design which needs a V-score, and want to submit it to JLCPCB. (The PCB can be used as one board, and there are traces on the bottom layer which connect the two sections. Alternatively the sections can be separated and re-connected via optional connectors provided in the layout.)
JLCPCB explicitly asks for V-cuts to be drawn in the outline layer, and states that otherwise they will miss them:
https://support.jlcpcb.com/article/68-instructions-for-ordering, section 7. But if I draw the V-cut across the board directly in Kicad's "edge cuts" layer, the DRC goes crazy with error messages about a malformed board outline, plus clearance violations from all the traces crossing the V-cut.
Is there a way to draw the V-cut in a separate layer in KiCad, and combine that layer with the edge cut layer during Gerber plotting?
Any other ideas on managing the V-cut in a way that is compatible with both, Kicad and JLCPCB, are appreciated too, of course!