Connecting two nets?

[bson]

I know it has been discussed for a long time, but did anything that you guys know get added to connect two nets without a footprint?  I could of course add a dummy footprint, like a single 0201 pad or something... but that gets silly and doesn't work on internal layers.

The obvious use case is there is VDD (say +3V3), which has a 22µF cap for a bunch of VDDIO's, which goes to 12 VDDIO_xx, each with its own 0.1µF cap.  Maybe a couple of them will have two.  They're all on +3.3V, but if via'd for example should NOT tie into the +3V3 power plane.  They can have their own zone under the part, inside a cutout from the +3V3 power plane.  In KiCAD, this gets really painful, and in this particular example the dummy pad doesn't work either because pads can't be on inner layers.  What's really desirable is for each power pin to have its own net, with its own cap(s) according to its needs, and then connect them to the main VDDIO net, which ties into the power plane.

But I'm not sure if I recall seeing anything actually added...

[Benta]

You use a "NetTie". That'll connect two differently named nets together.
Both in schematic (librery Device) and in PCB (library NetTie).
Or you make your own. It's not hard.

[WillTurner]

The original post requested a symbol-less footprint, which I don't think is possible. The following footprint code however, may help :-

Code: [Select]

#
# General Purpose Net Tie
# (C) Will Turner, 20 July 2024                       
#
# 1mm
#
#                                              || Change this each edit!
(module AAA_footprints:component-net-tie-1.0mm_04
  (layer F.Cu) (tedit 62AAB011)
  (descr "Nostromo Net Tie")
  (tags "Nostromo")

# Label from schematic editor.         || <- Also change this each edit!
(fp_text value component-net-tie-1.0mm_04 (at 0.00 -1.50)
  (layer B.SilkS)
  (effects
   (font (size 1 1) (thickness 0.153))
   (justify mirror)
  )
)                                         

# Component identifier - different way
(fp_text reference REF** (at 0.00 -1.50)
  (layer F.SilkS)
  (effects (font (size 1 1) (thickness 0.153)))
)

#
# Copper Splice
#

(fp_poly
  (pts
    (xy -1.30 -0.65)
    (xy  1.30 -0.65)
    (xy  1.30  0.65)
    (xy -1.30  0.65)
  )
  (layer F.Cu) (width 0)
)

(fp_poly
  (pts
    (xy -1.30 -0.65)
    (xy  1.30 -0.65)
    (xy  1.30  0.65)
    (xy -1.30  0.65)
  )
  (layer In1.Cu) (width 0)
)

(fp_poly
  (pts
    (xy -1.30 -0.65)
    (xy  1.30 -0.65)
    (xy  1.30  0.65)
    (xy -1.30  0.65)
  )
  (layer In2.Cu) (width 0)
)

(fp_poly
  (pts
    (xy -1.30 -0.65)
    (xy  1.30 -0.65)
    (xy  1.30  0.65)
    (xy -1.30  0.65)
  )
  (layer B.Cu) (width 0)
)

#
# Boundary, centre is the origin
#

(fp_line (start -2.2 0.9) (end -2.2 -0.9)
  (layer F.CrtYd) (width 0.05))
(fp_line (start 2.2 0.9) (end -2.2 0.9)
  (layer F.CrtYd) (width 0.05))
(fp_line (start 2.2 -0.9) (end 2.2 0.9)
  (layer F.CrtYd) (width 0.05))
(fp_line (start -2.2 -0.9) (end 2.2 -0.9)
  (layer F.CrtYd) (width 0.05))

#
# Through Holes
#
#   NB no mask exposure
#
(pad 1 thru_hole circle (at -1.2 0)
  (size 1.3 1.3)
  (drill 1)
  (layers *.Cu))
(pad 2 thru_hole circle (at 1.2 0)
  (size 1.3 1.3)
  (drill 1.0)
  (layers *.Cu)
)

)
#
# end
#

I'm currently working on a design to net-tie a bus, which will be a little more complicated, but is similar intent to the power bus proposed. Does anyone have better code that they are able to post?

[Doctorandus_P]

The use case here is not clear to me at all. If it's all the same +3.3V net then you can just draw some tracks and via's and connect it to the power plane in whatever form you like.

Power planes are also mostly deprecated. It's nearly always better to have more GND planes. although power planes can also act as GND planes, as the high frequency part can pass though the decoupling capacitors if they are well placed for the signal wires too.

Other options: You can change the net name of either a pad or a track segment by opening it's properties dialog and then select an existing name from the list, or enter a new name. (new net names can even be pushed back to the schematic as local labels).

You can also set the interactive router to "Highlight Collisions" and then "Allow DRC Violations". With these settings you can make as many shorts as you like.

[WillTurner]

Whether this is a correct use case or not, the following code is my first crack at a quad net tie. You would need a symbol with four pins, and since the footprint joins the four nets, the action happens at the symbol level. Something like power feeding in to one pin, and three output pins with separate bypass capacitors (or other isolation, as the case may be).
  Untested, but I think it will work. Code below.

Code: [Select]

#
# Quad Net Tie
# (C) Will Turner, 15 August 2024                       
#
# 1mm
#
#                                               || Change this each edit!
(module AAA_footprints:component-quad-tie-1.0mm_06
  (layer F.Cu) (tedit 62AAB011)
  (descr "Nostromo Net Tie")
  (tags "Nostromo")

# Label from schematic editor.          || <- Also change this each edit!
(fp_text value component-quad-tie-1.0mm_06 (at 0.00 -2.75)
  (layer B.SilkS)
  (effects
   (font (size 1 1) (thickness 0.153))
   (justify mirror)
  )
)                                         

# Component identifier - different way
(fp_text reference REF** (at 0.00 -2.75)
  (layer F.SilkS)
  (effects (font (size 1 1) (thickness 0.153)))
)

#
# Copper Splice, clockwise
#

(fp_poly
  (pts
    (xy -0.65 -0.65)
    (xy -0.65 -1.30)
    (xy  0.65 -1.30)

    (xy  0.65 -0.65)
    (xy  1.30 -0.65)
    (xy  1.30  0.65)

    (xy  0.65  0.65)
    (xy  0.65  1.30)
    (xy -0.65  1.30)

    (xy -0.65  0.65)
    (xy -1.30  0.65)
    (xy -1.30 -0.65)
  )
  (layer F.Cu) (width 0)
)


#
# Boundary, centre is the origin
#

(fp_line (start -2.2 2.2) (end -2.2 -2.2)
  (layer F.CrtYd) (width 0.05))
(fp_line (start 2.2 2.2) (end -2.2 2.2)
  (layer F.CrtYd) (width 0.05))
(fp_line (start 2.2 -2.2) (end 2.2 2.2)
  (layer F.CrtYd) (width 0.05))
(fp_line (start -2.2 -2.2) (end 2.2 -2.2)
  (layer F.CrtYd) (width 0.05))

#
# Through Holes
#
#   NB no mask exposure
#
(pad 1 thru_hole circle (at -1.2 0)
  (size 1.3 1.3)
  (drill 1)
  (layers *.Cu))
(pad 2 thru_hole circle (at 1.2 0)
  (size 1.3 1.3)
  (drill 1.0)
  (layers *.Cu))
(pad 3 thru_hole circle (at 0 -1.2)
  (size 1.3 1.3)
  (drill 1)
  (layers *.Cu))
(pad 4 thru_hole circle (at 0 1.2)
  (size 1.3 1.3)
  (drill 1.0)
  (layers *.Cu))

# The beginning of the end
)
#
# end
#

Note that you don't get away with these shenanigans without allocating some board space (!). If you wanted to join more than four nets, you might try some kind of comb arrangement.
Also, this link (https://www.eevblog.com/forum/kicad/handcrafted-footprints-for-kicad/) has some precursor material on whether the handcrafted code approach is a useful idea (or not).

[bson]

The use case here is not clear to me at all. If it's all the same +3.3V net then you can just draw some tracks and via's and connect it to the power plane in whatever form you like.

Yes, of course you can also make everything on the board a single net and draw whatever you like.

The point is, you're looking at 10 power pins and 35 capacitors, all on the +3.3V net.  The only way to wire it correctly is by constantly switching to the schematic and hunt for parts to see how they're supposed to be connected.  It's extremely tedious and error prone.

I like to use power planes, you're perfectly free not to.

[WillTurner]

Am I correct in assuming that you have a CPU package (maybe BGA) with lots of pins, and quite a few supply pins that need to be individually decoupled? I started to think along these lines, and about how you might lay out a kind of a busbar for a square package ...
  Then again, you could probably just use four of the quad net-tie's above, one located at each corner of the package. It probably wouldn't take up too much board space.

Edit: minor grammar.

[Doctorandus_P]

I still don't understand the problem. If you have this:

The point is, you're looking at 10 power pins and 35 capacitors, all on the +3.3V net. 

I like to use power planes, you're perfectly free not to.

If you want to use a power plane, that's OK, Decoupling caps do need correct locations of course, but you can simply start a short track from it, then place a via and press >[End]</b The via will connect to whatever layer the zone is automatically.

The only way to wire it correctly is by constantly switching to the schematic and hunt for parts to see how they're supposed to be connected.  It's extremely tedious and error prone.

Tedious to do it this way... maybe, but there are other options. Error prone certainly not. DRC will catch all missing connections. Designing a PCB without using DRC would be foolish.

For finding more connections for the same net, there are a whole lot of options.

• First there is the ratsnest. it connects unrouted pins or sections of a net to another unrouted section. You can make ratsnest lines curved or thicker to make them more visible.
• Net highlighting with the backtick key. Just hover over any section of a net and press the backtick (between [Esc] and [Tab] in the upper left corner of an US keyboard (Keys can be re-assigned
• Appearance Manager / Nets (tab page) You can set specific colors for nets so they are easily recognizable.
•   Show / Show Search panel and then the nets tab. Clicking a net highlights the whole net.
•   Show / Show Search panel and then the ratsnest tab. This gives you an overview of still to route connections.
•   Tools / Net Inspector lists nets in a separate window. Clicking on a net highlights it.

And there are probably more options. What works best for you depends on personal preferences and your goals.
Like in that other https://www.eevblog.com/forum/kicad/unlocking-footprints-in-8-0-4/ thread, there are probably many more things in KiCad you have yet to discover.

[bson]

But if everything is connected to +3.3V, what good is the rats nest?  It doesn't tell you which pins the 10uF caps go on, which the 1uF go on, and if some pins get multiple .1uF's.  This wouldn't be a problem if every supply pin had its own net, connected to the 3.3V net.

[Doctorandus_P]

In your original post you mention one 22uF capacitor and a bunch of 100nF capacitors. For generic decoupling the 22uF is a buffer capacitor and it does not matter much were it is on the PCB, it certainly does not have to be close to pins of an IC and it's usually placed somewhere near the input connector, or between a voltage regulator and the IC's that need power.

For the 100nF capacitors, It does not matter which goes where, as long as each set of power pins on your IC's has a decoupling capacitor. (For very fast logic demands are more stringent). Some people want to draw the schematic similar to the PCB layout, but I believe that is very bad practice. Schematic is for clarifying functionality while the PCB has very different rules such as conforming to EMC regulations and it has to actually work (Crosstalk and such). Placing generic decoupling capacitors near each IC on the schematic just distracts from the function of the schematic. I usually tug (nearly) all the decoupling capacitors away on a secondary sheet together with the power supply circuitry. The main circuit deals with function, the other sheet is for power delivery and "housekeeping".

But there are exceptions of course. It can be useful to indicate guard rings on the schematic (or they may be forgotton) When there is some special decoupling such as the analog power pin for an uC with ADC I also place it on the main sheet. In such cases use of a net tie can be an addition as a reminder to the PCB layout guy (even if it's yourself). If you do want to use a net tie, net ties with SMT pads are both smaller and easier to manufacture. More elaborate schemes can also include parts such as ferrite beads (and then a net tie is not needed).

Adding net ties to every decoupling capacitor is both a waste of time and a needless limitation during PCB design. If a PCB designer sees a row of 20 100nF capacitors on a schematic, and he places this as row of 20 capacitors on the PCB, then he really needs some re-education. Maybe join the Uyghurs in a Chinese concentration camp for half a year or so.

So now I understand your point of view. I don't agree with it, but I (probably) understand it.

[NF6X]

There is no way in KiCad to tie two nets together without using a net tie component with an associated footprint. At least in KiCad, net ties are best used sparingly where there is an electrical requirement like an isolated ground island, Kelvin connections, etc. that justifies dealing with their side-effect headaches. I would not recommend using net ties for the simple purpose of making it a little bit easier to have capacitor+pin adjacency match the schematic diagram. I think that doing so would cause more problems than it would solve. But hey, feel free to try it and see if it works for you.

Depending on personal preference, a designer may like to lump decoupling capacitors together on the schematic, or they may want to obsessively show each capacitor next to the pin it will actually be adjacent to. Some designers even like logic gate power pins to be hidden. Enough of the things I design have requirements to place certain components next to specific pins (i.e. power electronics, analog stuff, microwave, etc.) that I'm in the habit of using the obsessive approach even where it is not electrically necessary, so I do feel your frustration. But then, I tend to be obsessive about my schematics, anyway. It gets me compliments from other obsessive engineers who need to reference them, particularly compared to another engineer in the company whose work is pathologically sloppy.

I agree that the ratsnest does not help you match a specific capacitor to a specific pin on a specific part before you have the components placed the way you want them. I usually get capacitors at least close to the right component without specific effort because during initial component placement I'm in the habit of drag-selecting groups of related components in the schematic in order to get them selected in the schematic, and then using "Pack and Move Components" (should be mapped to the "P" hotkey) in the PCB to group them together. I usually stick each related group by itself somewhere off-board to see how it connects to other groups, and then start moving entire unrouted and randomly arranged groups to begin figuring out my placement strategy. Once I begin placing individual components within a group, the group at least contains the right capacitors (and only the right capacitors) for the IC(s) in that group. This will be less cumbersome if you have enough screen space to have the schematic and PCB tools open side by side.

[bson]

Actually, there's a very obvious, quick & dirty method I realized to do this: use net ties in the schematic, do the layout, then go back and remove the net ties, update the PCB, and add trace segments where the ties used to be.  Fill zones are slightly more cumbersome.

[Doctorandus_P]

Actually, there's a very obvious, quick & dirty method I realized to do this: use net ties in the schematic, do the layout, then go back and remove the net ties, update the PCB, and add trace segments where the ties used to be.  Fill zones are slightly more cumbersome.

Why do such a crazy convoluted complex and silly thing?
No, wait, don't answer, I don't even want to know.

[nctnico]

I know it has been discussed for a long time, but did anything that you guys know get added to connect two nets without a footprint?  I could of course add a dummy footprint, like a single 0201 pad or something... but that gets silly and doesn't work on internal layers.

The obvious use case is there is VDD (say +3V3), which has a 22µF cap for a bunch of VDDIO's, which goes to 12 VDDIO_xx, each with its own 0.1µF cap.  Maybe a couple of them will have two.  They're all on +3.3V, but if via'd for example should NOT tie into the +3V3 power plane.  They can have their own zone under the part, inside a cutout from the +3V3 power plane.  In KiCAD, this gets really painful, and in this particular example the dummy pad doesn't work either because pads can't be on inner layers.  What's really desirable is for each power pin to have its own net, with its own cap(s) according to its needs, and then connect them to the main VDDIO net, which ties into the power plane.

But I'm not sure if I recall seeing anything actually added...

I must say I find this an intriguing question. I don't have the answer but I do see the benefit. Every now and then I design circuit which would benefit from being able to give part of a net a specific status like it is a sub-net which different rules. This is handy for  when wanting traces which offer a little bit of extra inductance / resistance to form a filter with decoupling caps downstream. Or traces coming from a Kelvin connection which should be routed seperately.

If only you could specify some kind of connector object in the schematic which on the PCB translates to a connector point where the two nets may be connected without causing a DRC error.

[WillTurner]

If only you could specify some kind of connector object in the schematic which on the PCB translates to a connector point where the two nets may be connected without causing a DRC error.

This is precisely what I am doing (without the DRC error  ).
The connector object is an ordinary symbol with input pins, and output pins, fancy labels and the like. The magic actually happens in the footprint file (not the schematic as you were thinking). I previously gave an example in this thread of a quad net tie, which is a really simple example that more or less demonstrates the idea. To translate the idea to something closer to what you are thinking, you need to have more than one net-tie, connecting the input pins to the output. I can dig out a clear example if this explanation is not sufficient.

[Doctorandus_P]

If only you could specify some kind of connector object in the schematic which on the PCB translates to a connector point where the two nets may be connected without causing a DRC error.

This is exactly what a net tie does. It is it's sole specific usage and joy.

I am getting confused about the part of "using a net tie without using a net tie".

[nctnico]

If only you could specify some kind of connector object in the schematic which on the PCB translates to a connector point where the two nets may be connected without causing a DRC error.

This is precisely what I am doing (without the DRC error  ).
The connector object is an ordinary symbol with input pins, and output pins, fancy labels and the like. The magic actually happens in the footprint file (not the schematic as you were thinking). I previously gave an example in this thread of a quad net tie, which is a really simple example that more or less demonstrates the idea. To translate the idea to something closer to what you are thinking, you need to have more than one net-tie, connecting the input pins to the output. I can dig out a clear example if this explanation is not sufficient.

I understand your solution but now imagine putting a fat trace onto the net-tie which extends beyond the pad connection point. Then it will violate DRC rules because it overlaps with other traces connected to the net-tie. The same goes for a situation where you want to connect a variety of trace widths. You'll end up with a  myriad of situation specific net-tie footprints. That becomes more trouble than it is worth quickly. Especially if multiple people need to work on the design and understand what is going on exactly.

What is needed is some kind of 'magic zero-sized pad' which knows about 2 (or more) nets being joined and thus suppressing any DRC errors where it comes to shorting those nets at the 'magic pad'. That would be the most elegant solution.

[Doctorandus_P]

Handling of net ties has changed several times during KiCad's history.
It started as a straight out hack with KiCad not being able to anything (and thus simply ignoring) graphical objects on a copper layer.
And then, when KiCad improved and DRC  became aware of graphics on a copper layer, the "net tie" keyword was invented to suppress DRC violations caused by graphics in a net tie.
In KiCad V8, net ties changed again. Now you can define a list with pad numbers that are shorted inside the net tie footprint. I have not used net ties in KiCad V8 yet. It would require some testing to figure out how good this all works. And there is probably still room for improvement. If you know a part that does not work properly about the current implementation of net ties, or an idea of how they can be further improved, then make a feature request on gitlab.

But for the schematic, they will still be different pins with separate (possibly hidden) pin numbers. KiCad has to be able to distinguish the different nets.

[WillTurner]

I understand your solution but now imagine putting a fat trace onto the net-tie which extends beyond the pad connection point. Then it will violate DRC rules because it overlaps with other traces connected to the net-tie. The same goes for a situation where you want to connect a variety of trace widths. You'll end up with a  myriad of situation specific net-tie footprints. That becomes more trouble than it is worth quickly. Especially if multiple people need to work on the design and understand what is going on exactly.

As noted by Dr P, all of this may be moot if it is solved in KiCAD V8. (I am still running V5 point something.) This was always going to be a hack, and at the end of the day, hacking is exploring the tools, and bending them ... sometimes for the shear ( ) pleasure of seeing where they break.
  The hack to overcome thick traces breaking DRC might be to make the "output" pad large enough. We don't get away with these games without allocating board space!

  Also, there might be other uses for precisely defining an artifact on copper layers that is worth the trouble of climbing the learning curve. Exotic multi-layer antenna's anyone?

[bson]

The v8 net ties work, but still can't be used on internal layers.  So you still end up with two vias to an outer layer where the net tie footprint is placed, then go back to the schematic, remove the net tie, update the pcb, remove the extra vias and trace bits, and add an internal trace segment... But it's certainly better than going back and forth to the schematic!

[robzy]

When I recently desired this it was because I wanted to use net classes to ensure my high-amperage traces were thicker than low-amperage traces.

It was all 24V, but I didn't have room to make all of the 24V traces thicker.