Electronics > KiCad
Connecting two nets?
bson:
I know it has been discussed for a long time, but did anything that you guys know get added to connect two nets without a footprint? I could of course add a dummy footprint, like a single 0201 pad or something... but that gets silly and doesn't work on internal layers.
The obvious use case is there is VDD (say +3V3), which has a 22µF cap for a bunch of VDDIO's, which goes to 12 VDDIO_xx, each with its own 0.1µF cap. Maybe a couple of them will have two. They're all on +3.3V, but if via'd for example should NOT tie into the +3V3 power plane. They can have their own zone under the part, inside a cutout from the +3V3 power plane. In KiCAD, this gets really painful, and in this particular example the dummy pad doesn't work either because pads can't be on inner layers. What's really desirable is for each power pin to have its own net, with its own cap(s) according to its needs, and then connect them to the main VDDIO net, which ties into the power plane.
But I'm not sure if I recall seeing anything actually added...
Benta:
You use a "NetTie". That'll connect two differently named nets together.
Both in schematic (librery Device) and in PCB (library NetTie).
Or you make your own. It's not hard.
WillTurner:
The original post requested a symbol-less footprint, which I don't think is possible. The following footprint code however, may help :-
--- Code: ---#
# General Purpose Net Tie
# (C) Will Turner, 20 July 2024
#
# 1mm
#
# || Change this each edit!
(module AAA_footprints:component-net-tie-1.0mm_04
(layer F.Cu) (tedit 62AAB011)
(descr "Nostromo Net Tie")
(tags "Nostromo")
# Label from schematic editor. || <- Also change this each edit!
(fp_text value component-net-tie-1.0mm_04 (at 0.00 -1.50)
(layer B.SilkS)
(effects
(font (size 1 1) (thickness 0.153))
(justify mirror)
)
)
# Component identifier - different way
(fp_text reference REF** (at 0.00 -1.50)
(layer F.SilkS)
(effects (font (size 1 1) (thickness 0.153)))
)
#
# Copper Splice
#
(fp_poly
(pts
(xy -1.30 -0.65)
(xy 1.30 -0.65)
(xy 1.30 0.65)
(xy -1.30 0.65)
)
(layer F.Cu) (width 0)
)
(fp_poly
(pts
(xy -1.30 -0.65)
(xy 1.30 -0.65)
(xy 1.30 0.65)
(xy -1.30 0.65)
)
(layer In1.Cu) (width 0)
)
(fp_poly
(pts
(xy -1.30 -0.65)
(xy 1.30 -0.65)
(xy 1.30 0.65)
(xy -1.30 0.65)
)
(layer In2.Cu) (width 0)
)
(fp_poly
(pts
(xy -1.30 -0.65)
(xy 1.30 -0.65)
(xy 1.30 0.65)
(xy -1.30 0.65)
)
(layer B.Cu) (width 0)
)
#
# Boundary, centre is the origin
#
(fp_line (start -2.2 0.9) (end -2.2 -0.9)
(layer F.CrtYd) (width 0.05))
(fp_line (start 2.2 0.9) (end -2.2 0.9)
(layer F.CrtYd) (width 0.05))
(fp_line (start 2.2 -0.9) (end 2.2 0.9)
(layer F.CrtYd) (width 0.05))
(fp_line (start -2.2 -0.9) (end 2.2 -0.9)
(layer F.CrtYd) (width 0.05))
#
# Through Holes
#
# NB no mask exposure
#
(pad 1 thru_hole circle (at -1.2 0)
(size 1.3 1.3)
(drill 1)
(layers *.Cu))
(pad 2 thru_hole circle (at 1.2 0)
(size 1.3 1.3)
(drill 1.0)
(layers *.Cu)
)
)
#
# end
#
--- End code ---
I'm currently working on a design to net-tie a bus, which will be a little more complicated, but is similar intent to the power bus proposed. Does anyone have better code that they are able to post?
Doctorandus_P:
The use case here is not clear to me at all. If it's all the same +3.3V net then you can just draw some tracks and via's and connect it to the power plane in whatever form you like.
Power planes are also mostly deprecated. It's nearly always better to have more GND planes. although power planes can also act as GND planes, as the high frequency part can pass though the decoupling capacitors if they are well placed for the signal wires too.
Other options: You can change the net name of either a pad or a track segment by opening it's properties dialog and then select an existing name from the list, or enter a new name. (new net names can even be pushed back to the schematic as local labels).
You can also set the interactive router to "Highlight Collisions" and then "Allow DRC Violations". With these settings you can make as many shorts as you like.
WillTurner:
Whether this is a correct use case or not, the following code is my first crack at a quad net tie. You would need a symbol with four pins, and since the footprint joins the four nets, the action happens at the symbol level. Something like power feeding in to one pin, and three output pins with separate bypass capacitors (or other isolation, as the case may be).
Untested, but I think it will work. Code below.
--- Code: ---#
# Quad Net Tie
# (C) Will Turner, 15 August 2024
#
# 1mm
#
# || Change this each edit!
(module AAA_footprints:component-quad-tie-1.0mm_06
(layer F.Cu) (tedit 62AAB011)
(descr "Nostromo Net Tie")
(tags "Nostromo")
# Label from schematic editor. || <- Also change this each edit!
(fp_text value component-quad-tie-1.0mm_06 (at 0.00 -2.75)
(layer B.SilkS)
(effects
(font (size 1 1) (thickness 0.153))
(justify mirror)
)
)
# Component identifier - different way
(fp_text reference REF** (at 0.00 -2.75)
(layer F.SilkS)
(effects (font (size 1 1) (thickness 0.153)))
)
#
# Copper Splice, clockwise
#
(fp_poly
(pts
(xy -0.65 -0.65)
(xy -0.65 -1.30)
(xy 0.65 -1.30)
(xy 0.65 -0.65)
(xy 1.30 -0.65)
(xy 1.30 0.65)
(xy 0.65 0.65)
(xy 0.65 1.30)
(xy -0.65 1.30)
(xy -0.65 0.65)
(xy -1.30 0.65)
(xy -1.30 -0.65)
)
(layer F.Cu) (width 0)
)
#
# Boundary, centre is the origin
#
(fp_line (start -2.2 2.2) (end -2.2 -2.2)
(layer F.CrtYd) (width 0.05))
(fp_line (start 2.2 2.2) (end -2.2 2.2)
(layer F.CrtYd) (width 0.05))
(fp_line (start 2.2 -2.2) (end 2.2 2.2)
(layer F.CrtYd) (width 0.05))
(fp_line (start -2.2 -2.2) (end 2.2 -2.2)
(layer F.CrtYd) (width 0.05))
#
# Through Holes
#
# NB no mask exposure
#
(pad 1 thru_hole circle (at -1.2 0)
(size 1.3 1.3)
(drill 1)
(layers *.Cu))
(pad 2 thru_hole circle (at 1.2 0)
(size 1.3 1.3)
(drill 1.0)
(layers *.Cu))
(pad 3 thru_hole circle (at 0 -1.2)
(size 1.3 1.3)
(drill 1)
(layers *.Cu))
(pad 4 thru_hole circle (at 0 1.2)
(size 1.3 1.3)
(drill 1.0)
(layers *.Cu))
# The beginning of the end
)
#
# end
#
--- End code ---
Note that you don't get away with these shenanigans without allocating some board space (!). If you wanted to join more than four nets, you might try some kind of comb arrangement.
Also, this link (https://www.eevblog.com/forum/kicad/handcrafted-footprints-for-kicad/) has some precursor material on whether the handcrafted code approach is a useful idea (or not).
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