Author Topic: Help with KiCAD Footprint for Power SOIC-8  (Read 3752 times)

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Offline LoveLaika

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Help with KiCAD Footprint for Power SOIC-8
« on: July 27, 2021, 09:07:41 pm »
I'm using the LM7372 dual op-amp IC as part of my circuit. It comes in a Power-SOIC-8 package with an exposed pad, and I need some help implementing it in KiCAD.

To start off, I uploaded Digikey's library of KiCAD footprints to use as a reference and modified it a bit to match the LM7372 datasheet (shown in image below). I have two questions.

1. The exposed center pad has to be left electrically floating. Since it has vias, I want to add a small copper pour section to form an isolated copper island within my ground plane that is connected to the exposed pad. How do I do that?

2. The original footprint had two square rectangle pads for the exposed pad, with one pad being longer than the other. I deleted the long one as shown in the picture, and I adjusted the center pad so it is the size of what is recommended in the datasheet. For those who have used this type of component before, should I make the exposed pad longer than normal, or should I just keep it the fixed size?


https://www.ti.com/lit/ds/symlink/lm7372.pdf
 

Offline phil from seattle

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #1 on: July 28, 2021, 12:41:00 am »
The datasheet shows a different footprint than you describe.  I think I'd follow the datasheet.

There is probably a better way but I would add a pad to the footprint for the exposed pad, add a pin for it in the symbol. In the schematic, connect it to something (so you get a net, maybe create a symbol for that), in the PCB create a filled zone (or zones) for that net and draw it however you like.  Turn off thermal relief for the pad. 

 

Offline LoveLaika

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #2 on: July 28, 2021, 01:19:39 am »
Thanks for replying. If I may, whats different about the footprint? Its mildly different with more via holes and the pads a bit longer, but otherwise, the dimensions are right, and TI's 3D model fits it.

I tried adding a copper pour tied to the exposed pad net on my ground pour,but it didnt isolate from the ground plane.
 

Offline phil from seattle

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #3 on: July 28, 2021, 04:02:34 am »
You described multiple pads.

You need to set the net of the Copper Zone.  I'd guess the one you drew is Gnd.  The screen shot shows a board I made that has GndA - you could use that.  It doesn't connect to Gnd.





 

Offline LoveLaika

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #4 on: July 28, 2021, 04:09:27 am »
I did do that. My board has a large copper pour tied to GND as the net. I then made another copper pour to fit over that GND pour and tied it to the net as indicated by the exposed pad, but it never showed.
 

Offline phil from seattle

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #5 on: July 28, 2021, 05:54:46 pm »
I don't think you can overlap pours for different nets.  Set a moderately coarse grid and draw an opening in the ground pour.  You might need to split Gnd into 2 pours.
 

Offline mf_ibfeew

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #6 on: July 28, 2021, 09:29:16 pm »
>My board has a large copper pour tied to GND as the net.
>I then made another copper pour to fit over that GND pour and tied it to the net as indicated by the exposed pad, but it never showed.
We don't know your Kicad version.
I'm working actually with v5.99 and overlapping copper pours (filled zones) are possible.
You have to take care to the priority-level, both zones need different values, the inner zone (connecting to your exposed-Pad) with higher priority than the outer GND-zone.
 

Offline LoveLaika

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #7 on: July 28, 2021, 09:34:48 pm »
I'm running on KiCAD version (5.1.9)-1, release build. Below is the version info:

Application: KiCad
Version: (5.1.9)-1, release build
Libraries:
    wxWidgets 3.0.5
    libcurl/7.71.0 OpenSSL/1.1.1g (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.3.0 libpsl/0.21.0 (+libidn2/2.3.0) libssh2/1.9.0 nghttp2/1.41.0
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    wxWidgets: 3.0.5 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.73.0
    OpenCASCADE Community Edition: 6.9.1
    Curl: 7.71.0
    Compiler: GCC 10.2.0 with C++ ABI 1014
 

Offline phil from seattle

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #8 on: July 28, 2021, 09:45:17 pm »
It also works in 5.1.9 (what I'm running).  Good to know.  You will also need to set pad connections to Solid (default is thermal relief).
 

Offline LoveLaika

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Re: Help with KiCAD Footprint for Power SOIC-8
« Reply #9 on: July 28, 2021, 10:02:12 pm »
Thanks. I see what the problem is now. It's a combination of zone priorities and the pad's connection to copper zones. For me, the default was 'from parent footprint'. When I changed it 'Solid', it fills in as expected while it's in the designated zone area. Problem solved, but why is setting the pad connection necessary?
 


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