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Digital logic simulation tied to KiCad?

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ebastler:
I'm making progress in my transition from Eagle to KiCad, and have now completed my first major schematic. (A hierarchical schematic with 10 sheets in total. Eeschema handled that nicely, with some unexpected glitches which I need to try and reproduce before posting/asking about them.)

This is a vintage computer design with about sixty 74HC series chips (a scaled-down functional model of Turing's Pilot ACE). Before I start laying out the PCB, I would like to do some plausibility testing via simulation. I realize that NGSpice can be used with KiCad, but I don't need analog-level simulation, and a circuit of that size would probably be a bit much for NGSpice. Also, I would like a better view of many digital signals at a time, and ideally a simulator which already knows the standard 74' series gates, flip-flops, and shift registers.

Is there a (preferably free) digital logic simulation software which can import the KiCad netlists?

Doctorandus_P:
Have you done the simple ERC check in Eeschema?
It checks simple things such as outputs of several IC's connected together.

Eeschema can also export the netlist in 4 different formats (Native, OrcadPCB2, CadStar, Spice) and it also accepts plugins for other formats. You could also write some script to transmorph KiCads output into some other netlist format.  they are all text based and pretty simple to modifiy with a scripting language.

I'm not into digital simulation myself, but KiCad is getting quite popular, so if you find a decent tool for digital simulation there is a reasonable chance it can work with KiCad, or you can ask on their forum how to go forward.

ebastler:
Yes, I have done the ERC check and the schematic passes that. (After I had fixed quite a few sloppy mistakes of mine...)

I am hoping to do a next level of checks -- to find mistakes in my thought process when designing the circuit. For example, the whole Pilot ACE computer is based on bit-serial logic, so it's easy to be "off by one bit" when starting and ending operations. That's where I hope to get more confidence via simulating, before I commit to layout, PCB production and populating a board.

So far I have not found a promising digital simulation software at all in a first (superficial) search. The ones I found seem geared towards small basic circuits, for educational purposes. There obviously are "serious" simulators as part of the FPGA development suites, but at first glance they seem pretty deeply embedded into the respective FPGA workflows. So I'm hoping someone has a recommendation for something that's known to work stand-alone, and with the KiCad netlists.

Bassman59:
The only reasonable concept I can see for simulating 74-series circuit designs is to have a VHDL model of each part linked to the symbol, in much the way SPICE models are linked to symbols, and then have a net-lister build the interconnections based on what you drew and spit out a "board-level" VHDL entity file. Then you can create a VHDL test bench and use ghdl or other simulator.

None of that exists, of course, but it doesn't seem to be "difficult." The trick is to get a developer interested in implementing this.

julian1:
Following the suggestion to use HDL to simulate (maybe with a translation layer from kicad netlists), there's at least a verilog implementation for 74hc logic,

https://github.com/TimRudy/ice-chips-verilog

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