What are you concerned about - the logic itself or lower level electronic interactions (like fan outs, capacitive loads and so on)? There are a number of 74 logic simulators that will allow you to test the logic.
I think I would just breadboard subcomponents where I wasn't sure. A logic analyzer is a must for this. I'd also use something like an Arduino or Teensy for injecting test inputs.
What I would hope to verify via simulations is the logic itself, optionally including the effect of nominal gate delays. I have not found any solution where a logic simulator could be fed directly from the KiCad schematic or netlist though. Re-entering the logic description in VHDL and using the logic simulation in, say, the Xilinx FPGA IDE may be my best bet here?
If you want to build a model of your circuit and include nominal gate delays, then the VHDL approach will work. Creating models for the various 74xxx parts isn't all that hard, and you can embed the gate and other delays in the models. Estimating board-level effects (capacitance of traces and loading which affect timing) might be more complicated, but there's nothing stopping you from using standard VHDL transport delay models for the traces.
You can use any of the FPGA vendors' free ModelSim, or you can use ghdl, and off you go. I'm sure you can use Vivado's simulator, too, but it's been awhile since I was in Xilinx-land.
NB: you should probably use worst-case timing parameters. You can be clever and add generics to each model which specify MIN, TYP and MAX delays and at the top level of your simulation you choose which to use.
(VITAL does all of that, but it's horribly complicated and nobody really understands it!)
I have reached the same conclusion regarding physical breadboarding. I'll do that for some components where I am concerned about timing details, startup behavior or such.
Breadboards add parasitics that won't be present in a proper PCB layout, so be aware.