Digital logic simulation tied to KiCad?

[ebastler]

I'm making progress in my transition from Eagle to KiCad, and have now completed my first major schematic. (A hierarchical schematic with 10 sheets in total. Eeschema handled that nicely, with some unexpected glitches which I need to try and reproduce before posting/asking about them.)

This is a vintage computer design with about sixty 74HC series chips (a scaled-down functional model of Turing's Pilot ACE). Before I start laying out the PCB, I would like to do some plausibility testing via simulation. I realize that NGSpice can be used with KiCad, but I don't need analog-level simulation, and a circuit of that size would probably be a bit much for NGSpice. Also, I would like a better view of many digital signals at a time, and ideally a simulator which already knows the standard 74' series gates, flip-flops, and shift registers.

Is there a (preferably free) digital logic simulation software which can import the KiCad netlists?

[Doctorandus_P]

Have you done the simple ERC check in Eeschema?
It checks simple things such as outputs of several IC's connected together.

Eeschema can also export the netlist in 4 different formats (Native, OrcadPCB2, CadStar, Spice) and it also accepts plugins for other formats. You could also write some script to transmorph KiCads output into some other netlist format.  they are all text based and pretty simple to modifiy with a scripting language.

I'm not into digital simulation myself, but KiCad is getting quite popular, so if you find a decent tool for digital simulation there is a reasonable chance it can work with KiCad, or you can ask on their forum how to go forward.

[ebastler]

Yes, I have done the ERC check and the schematic passes that. (After I had fixed quite a few sloppy mistakes of mine...)

I am hoping to do a next level of checks -- to find mistakes in my thought process when designing the circuit. For example, the whole Pilot ACE computer is based on bit-serial logic, so it's easy to be "off by one bit" when starting and ending operations. That's where I hope to get more confidence via simulating, before I commit to layout, PCB production and populating a board.

So far I have not found a promising digital simulation software at all in a first (superficial) search. The ones I found seem geared towards small basic circuits, for educational purposes. There obviously are "serious" simulators as part of the FPGA development suites, but at first glance they seem pretty deeply embedded into the respective FPGA workflows. So I'm hoping someone has a recommendation for something that's known to work stand-alone, and with the KiCad netlists.

[Bassman59]

The only reasonable concept I can see for simulating 74-series circuit designs is to have a VHDL model of each part linked to the symbol, in much the way SPICE models are linked to symbols, and then have a net-lister build the interconnections based on what you drew and spit out a "board-level" VHDL entity file. Then you can create a VHDL test bench and use ghdl or other simulator.

None of that exists, of course, but it doesn't seem to be "difficult." The trick is to get a developer interested in implementing this.

[julian1]

Following the suggestion to use HDL to simulate (maybe with a translation layer from kicad netlists), there's at least a verilog implementation for 74hc logic,

https://github.com/TimRudy/ice-chips-verilog

[bson]

ngspice includes xspice, which offers digital simulation.  I've never used it though, so can't offer much more.
http://ngspice.sourceforge.net/xspice.html
http://ngspice.sourceforge.net/xspice/Xspice_Users_Manual.pdf

[phil from seattle]

What are you concerned about - the logic itself or lower level electronic interactions (like fan outs, capacitive loads and so on)? There are a number of 74 logic simulators that will allow you to test the logic.

I think I would just breadboard subcomponents where I wasn't sure.  A logic analyzer is a must for this.  I'd also use something like an Arduino or Teensy for injecting test inputs.

[ebastler]

What are you concerned about - the logic itself or lower level electronic interactions (like fan outs, capacitive loads and so on)? There are a number of 74 logic simulators that will allow you to test the logic.

I think I would just breadboard subcomponents where I wasn't sure.  A logic analyzer is a must for this.  I'd also use something like an Arduino or Teensy for injecting test inputs.

What I would hope to verify via simulations is the logic itself, optionally including the effect of nominal gate delays. I have not found any solution where a logic simulator could be fed directly from the KiCad schematic or netlist though. Re-entering the logic description in VHDL and using the logic simulation in, say, the Xilinx FPGA IDE may be my best bet here?

I have reached the same conclusion regarding physical breadboarding. I'll do that for some components where I am concerned about timing details, startup behavior or such.

[Bassman59]

What are you concerned about - the logic itself or lower level electronic interactions (like fan outs, capacitive loads and so on)? There are a number of 74 logic simulators that will allow you to test the logic.

I think I would just breadboard subcomponents where I wasn't sure.  A logic analyzer is a must for this.  I'd also use something like an Arduino or Teensy for injecting test inputs.

What I would hope to verify via simulations is the logic itself, optionally including the effect of nominal gate delays. I have not found any solution where a logic simulator could be fed directly from the KiCad schematic or netlist though. Re-entering the logic description in VHDL and using the logic simulation in, say, the Xilinx FPGA IDE may be my best bet here?

If you want to build a model of your circuit and include nominal gate delays, then the VHDL approach will work. Creating models for the various 74xxx parts isn't all that hard, and you can embed the gate and other delays in the models. Estimating board-level effects (capacitance of traces and loading which affect timing) might be more complicated, but there's nothing stopping you from using standard VHDL transport delay models for the traces.

You can use any of the FPGA vendors' free ModelSim, or you can use ghdl, and off you go. I'm sure you can use Vivado's simulator, too, but it's been awhile since I was in Xilinx-land.

NB: you should probably use worst-case timing parameters. You can be clever and add generics to each model which specify MIN, TYP and MAX delays and at the top level of your simulation you choose which to use.

(VITAL does all of that, but it's horribly complicated and nobody really understands it!)

I have reached the same conclusion regarding physical breadboarding. I'll do that for some components where I am concerned about timing details, startup behavior or such.

Breadboards add parasitics that won't be present in a proper PCB layout, so be aware.

[phil from seattle]

Breadboards add parasitics that won't be present in a proper PCB layout, so be aware.

True but if you are just trying to get the logic correct, breadboard is pretty quick and easy. I would never try to build anything beyond simple circuits that way though.

[hamster_nz]

Might be helpful to include lots of probe-friendly test points.

Is there any sort of standard footprint for something you can razor through and then add a bodge wire either side?

[ebastler]

Might be helpful to include lots of probe-friendly test points.

Is there any sort of standard footprint for something you can razor through and then add a bodge wire either side?

Good point! I had been thinking about the process of bringing the complete board to life, and have also concluded that I need a way to feed test signals to the individual functional modules to check them out. The Pilot ACE design is so tightly integrated, and the clock needs to keep ticking at full rate at all times to keep the ultrasonic delay line memory alive -- it is not very debug-friendly.

I am using larger SMD packages only, SOIC and SOT-23, so I can still lift individual pins and solder bodge wires to pin and pad. But providing some additional "breakpoints" via suitable pads is a good idea. The standard pre-connected jumper footprint (2 pads with a short trace connecting them) should work nicely.

I have also provided through-hole pads as testpoints here and there, with through-hole ground pads next to them -- to stick in a "naked" probe tip and ground spring. Works well in my experience, without the need for space-consuming probe holders. Although it's a great way to break the pointed tips by accident...

[Doctorandus_P]

Might be helpful to include lots of probe-friendly test points.

Is there any sort of standard footprint for something you can razor through and then add a bodge wire either side?

In KiCad there are a bunch of "SolderJumper" footprints. They come in two and three pad variants, ans also "NO" and "NC". You can cut the "NC" version open with something sharp, and close them again with a blob of solder.
They look like:

[nick.theboatman]

So casting back into the dark and distant... I was designing a gate array. We built a simulator with TTL stuff - approx 120 chips - and put the design down on a PCB. Schematic capture using FutureNET schematics on PCs and SciCARDS PCBs running on a VAX and a bit of code I hacked together to do netlist translation. You can get scope probes and a logic analyser onto a PCB. When we were satisfied with the design we translated the nets to the format needed for the simulator suite (I forget which - also ran on the VAX) to get the dynamic response / delays to verify the gate array routing. Pain in the arse. I chucked that out and used a Philips-source PC-based logic simulator. Worked a treat, 1980's-style

At the next company I used Xilinx LCAs with the Xilinx simulator. We used ACE (if I remember) on a Sparc or suchlike. Also 1980s.

At the next company I introduced OrCAD Schematics and CADStar PCBs again with home-cooked netlist translation. We also used a mix of LCAs and PCB layout so did netlist translators to do either LCA design or PCB design. 1990s.

So while I hate to say it, you could go the other way round: build the design in an LCA and then back-engineer it to TTL devices. You can bugger around with the LCA design to your hearts content with no risk, looking at pinned-out nets with an analyser. When you are happy with it take it back to gates and MSI functions and lay a board.

Ok I'm feeling all nostalgic now.

[ebastler]

Thank you for sharing the story!

I eventually took the plunge a few weeks ago and decided to have PCBs made without prior simulation, after several more days of staring at the schematics... Just received the boards before the past weekend, added the through-hole parts and started to check things out. Looking good so far; I did not find any major blunders yet. (But have not yet gotten to the point where I try to run programs.)

Picture attached. Once I actually get this up and running I will post a bit more in the Vintage Computing section.