That allows for some degree of consistency, as different vendors will use slightly different recommended packages for the same package name, e.g., SOIC-8 has several variations. If the difference is significant, I will append the package name with that vendor, e.g., "CON-FFP-0.5_16P_MOLEX" vs. "CON-FFP-0.5_16P_TE" and use that as a device variant.
This statement is actually misguided (or outdated).
Iff the package has the same measurement and the same tolerance (Generally true for two JEDEC compliant packages with the same JEDEC identifier) then the same footprint can be used in the same manufacturing process. It does not matter what the part manufacturer suggests!
Your connector example might stretch this a bit but lets go along with it. Most FFP connectors can connect to the same pattern on the flexible PCB (cable) side (even if the ideal pattern is slightly different). This is because there are standardized cables out there and every manufacturer wants to be compatible to them. Meaning you can use the exact same footprint for all your flexible boards no matter what the exact connector is (assuming they are of the same type: so pitch, pin count and side count are equal). But the solder interface is different for every connector order number (even two connectors by molex will be incompatible). Which is why you will then have one footprint per order number not one per manufacturer. Even if there are two footprint compatible ones as it will be hard to encode the required parameters in a sensible footprint name.Lets get back to IC footprints: Part manufacturers simply use their internal assumption of what the manufacturing process of a user might be to derive their suggested footprint from some standard (most likely IPC). Most modern datasheets will also include a note that a footprint derived from IPC-7351x is also applicable exactly because they know that their assumption will not fit the process of all their users.
The suggested footprint will be good enough for low volume production where yield is not critical so it is good enough for most of us. But so is any IPC derived footprint with reasonable parameters so you can exchange the suggested footprint by for example TI with the one by Analog as long as the dimensions of the package itself are identical.
This is actually the reason why the official KiCad library as well as the eagle footprint generator ignore the manufacturer suggestion completely and use only the package dimension including their tolerances and IPC equations to derive footprints.
The thing is that a scalable lib makes it easy to change your IPC parameters for a given package if your manufacturing parameters change. That will be quite hard if the same footprint is in multiple libraries as it is then quite easy to miss one of these copies. This is why I think KiCads approach is simply the better one.
Plus even with KiCads approach you can still make one footprint per manufacturer if you really want to (just make a SOIC lib for TI and one for Analog). However, the only reason i can think of would be to silence a superior who has no clue and wants every used footprint to follow the datasheet suggestion instead of allowing the use of modern industry standards.
By the way there are of course exceptions. Examples are MEMS components and high frequency parts which might not be well served with a footprint derived from the general industry standard. Here we use the datasheet suggestion even in the official KiCad library simply because there are other considerations to take into account that are not covered by IPC.
For MEMS it is avoiding of mechanical stress and for high frequency it is the exact impedance.