Fill Properties SMD Pads

[ciikucli]

I created a ground fill on the ground layer and told it to connect the GND net to itself. I see the thermal relief on the through hole GND pins, but I was wondering if it connected the SMD pads as well. I'd like to know if I need vias for every connection.

Also, is it standard practice to add fills to the top and bottom layers of the board once you finish?

[HackedFridgeMagnet]

If you plot the file into gerbers you will be able to see what pads it actually connects too.
If everything is correct it will fill to the pads and vias that are connected to the same net but it wont connect to pads on other nets.
Of course if something is physically in the way it wont be able to connect, and you may be left with islands. You will may need to put some extra vias in the board to connect these islands.

[ciikucli]

Here's an image of the a couple pads that are supposed to be connected to GND. The two unconnected D19 gray pads need to go to ground.


I'm guessing that since the ground fill is on layer 3 and the pads are on the top layer that they did not connect. If this is accurate, what's the best way to connect the voltage regulators to the GND layer?

[HackedFridgeMagnet]

I'm guessing that since the ground fill is on layer 3 and the pads are on the top layer that they did not connect. If this is accurate, what's the best way to connect the voltage regulators to the GND layer?

Yes I was assuming the fill and the pad were on the same layer.

All you need to do is run a small track out from the pad and place a via. The via will connect to all layers that are incident with pads, tracks or fills on the same net.
You can actually put a via in the pad itself if you want to which is electrically better but i find looks a bit confusing and soldering may not be optimal.
On other layers where the via is on a different net to the fill, the fill process will leave a gap around the via.

[marshallh]

There is/was an outstanding bug in Kicad where stitching vias would randomly come unconnected and isolated from the net, and then fills would avoid the same net

[HackedFridgeMagnet]

That bug might still be there, and in my ignorance I didn't really consider it a bug. It might be code that just hasn't been written.

As a work around I have been connecting the stiching vias with dummy tracks anyway, just to make sure they are on the correct net and do fill properly. The dummy tracks then get filled over and so the the copper ends up being exactly the same.

[c4757p]

There is/was an outstanding bug in Kicad where stitching vias would randomly come unconnected and isolated from the net, and then fills would avoid the same net

I have a feeling this bug is actually a minefield of bad code. I've had problems with tracks and vias randomly losing their net  since the beginning, and the situation has been gradually improving. Gradual progress rather than suddenly fixing it tells me somebody really screwed up the net code....

[HackedFridgeMagnet]

I must admit I haven't really gone through the source code, but my initial feeling is that this is an overlooked architectural/design issue, that would take a lot of changes to fix.
I wouldn't think it is near the top of the todo list either.

[ciikucli]

All this makes me a little bit anxious. Is it still worth learning this program, or should I move to one of the bigger ones like eagle?

[HackedFridgeMagnet]

I just did a kicad quick code review yesterday. Just to see what it looked like.
https://www.eevblog.com/forum/eda/kicad-code-review-after-a-quick-poke-around-in-the-source/

I am very happy to use Kicad, I tried to start on Eagle a couple of times but stopped, I was probably a bit prejudiced against it because it looked like a Win98 UI.
I am currently using Kicad professionally, I am not sure if that means much.

Probably the only problems I have with Kicad are
1. I end up having to create a lot of my own components for the library both schematic and pcb because the Kicad libs are not as comprehensive as Eagle, but it doesn't take long.
2. The changing the track widths and spacings and its integration with DRC I find annoying. The main problem stems from having a net that has two settings. I am not sure the best way to manage this. eg. Make a track small to go into a 0.5mm pitch pin but then widen out if it has to go a long way. I end up having to defeat the DRC to get around this.

The issue with via stiching is really a non issue. You have to identify a via as part of a particular net anyway, the easiest way to do this is to join a dummy track to it. I don't know how they do it in Altium, but it is really not a problem in Kicad and so I doubt they will change it.

One piece of advice I would give to you no matter what EDA you choose is to put Source control (such as SVN) onto your library files and your projects. It will save you a lot of grief.