Inner Copper Clearances?

[LoveLaika]

My PCB fab house has different inner and outer copper clearance requirements. They require a copper-to-board edge clearance of 10 mils (0.254 mm) on the outer layer and 15 mils (0.381 mm) on inner layers. How do you change the design rules to account for this? I see an option for this in the constraints section of the design rules labeled as "copper to edge clearance", but this affects all layers. Is there a way to set this in the design rules automatically? The only other way I could think of is to set it for largest clearance or to just adjust the copper pour zones.

[6313oscar]

You could make your own costum DRC rule for this:

Kicad PCB editor -> Board setup -> Custom DRC rules

Code: [Select]

(version 1)
(rule "outer layer clearance"
(layer outer)(constraint edge_clearance (min 0.254mm)))

(rule "Inner layer clearance"
(layer inner)(constraint edge_clearance (min 0.381mm)))