EEVblog Electronics Community Forum
Electronics => PCB/EDA/CAD => KiCad => Topic started by: Miti on June 29, 2020, 12:21:40 pm
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I wanted to try a design with BGA and since the free Eagle doesn't allow 4 layers, I tried Kicad 5.1.6. FPGA library is from SnapEDA. I get some circles around the pads which I believe are keep-out areas that I cannot get rid of. DRC rules are JLCPCB minimums.
How ready is Kicad for fine pitch BGAs?
This is the second time that I looked at Kicad and the first impression (or the second) is not very good. It seems awkward to me, a long time user of Eagle.
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You can get rid of them visually or effectively, look here https://www.eevblog.com/forum/kicad/kicad-lock-component/msg3096015/#msg3096015 (https://www.eevblog.com/forum/kicad/kicad-lock-component/msg3096015/#msg3096015)
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Might be to fine pitch BGA for JLCPCB
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If the software is try to prevent you from breaking your design rules, seems like a good thing to me? :-//
The outline around your BGA pads is the clearance rule you've set. Given that they're intersecting with one another, your clearance isn't small enough. Either check your clearance rules, or if they're correct JLC can't manufacturer your specs.
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You can get rid of them visually or effectively, look here https://www.eevblog.com/forum/kicad/kicad-lock-component/msg3096015/#msg3096015 (https://www.eevblog.com/forum/kicad/kicad-lock-component/msg3096015/#msg3096015)
Removing the DRC sounds like a really bad idea to me.
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Might be to fine pitch BGA for JLCPCB
I don't think it is the case, my BGA is Altera UBGA484, pad is 0.5mm, pitch is 0.8mm, pad to pad clearance is 0.3mm.
JLC BGA capabilities for 4-6 layers, min pad 0.25mm, pad to pad clearance 0.127mm.
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You can get rid of them visually or effectively, look here https://www.eevblog.com/forum/kicad/kicad-lock-component/msg3096015/#msg3096015 (https://www.eevblog.com/forum/kicad/kicad-lock-component/msg3096015/#msg3096015)
Removing the DRC sounds like a really bad idea to me.
I don't want to remove DRC rules. I just wanted to know where is that circle defined and what rule I'm breaking.
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I looked a bit closer, I think fanning it out would be a challenge, definitely not possible to fan out many I/Os on a 4 layer board with JLC or PCBWay capabilities.
Oh, well...
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Sorry, I'm running a nightly build, so the UI for DRC is going to look a little different, nor would I recommend running nightly either.
To get into the DRC menu, you want to hit this button in the toolbar.
From there, you can set up your design rules via "constraints" (What KiCAD will be checking against to see if your board is able to be manufactured) and your "Net Classes" (I haven't played around with this much before, but it will be for applying design rules to certain nets eg. rules for high voltage traces). You should have a setup roughly what I have, which will allow you to just get a via in between 0.4mm wide BGA pads like so.
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The problem is that I have 0.35mm between pads. If I squeeze a 0.127mm trace in between two pads, I violate JLC’s minimum clearance requirements.
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@knapik the DRC system has been totally reworked in nightly. So please do not confuse users with the new unstable stuff that is currently rabidly changing.
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For reference KiCad version 5 can only define clearances on the netclass, footprint or pad level. All of that is found under file->board setup in KiCad 5.1.6 (the same is true for all 5.1.x releases including future ones, as minor releases are not allowed to change KiCads interface or behaviour)
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The problem is that I have 0.35mm between pads. If I squeeze a 0.127mm trace in between two pads, I violate JLC’s minimum clearance requirements.
Then you need to find a different board house.
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I have been making boards with 0.8mm pitch BGAs with KiCAD since V4.0.7 (around late 2017), and the the 5.1.6 version is more than capable of doing fine-pitch BGAs. I use OSHpark for all my prototypes and have never had any problems.
I don't think it is the case, my BGA is Altera UBGA484, pad is 0.5mm, pitch is 0.8mm, pad to pad clearance is 0.3mm.
JLC BGA capabilities for 4-6 layers, min pad 0.25mm, pad to pad clearance 0.127mm.
You are looking at the BGA *package*, not the footprint. The 0.5mm spec is the size of the solder-ball, *NOT* the footprint pad for the ball. The recommended ball-pad is 0.4mm for a 0.8mm ball-pitch, non-solder-mask-defined NSMD. You can get away with *one* 0.127mm (5mil) trace between those pads and be within the capabilities of most board-house's standard specs (i.e. not the high cost or special features). Your vias need to be 0.46mm dia / 0.25mm hole (18mil / 10mil) or smaller to be able to dog-bone the pads.
The problem is that I have 0.35mm between pads. If I squeeze a 0.127mm trace in between two pads, I violate JLC’s minimum clearance requirements.
Actually, you will have 0.4mm between the pads, enough for one 0.127mm trace at standard-specs.
I don't want to remove DRC rules. I just wanted to know where is that circle defined and what rule I'm breaking.
You have to adjust your DRC-rules based on the specifications you are working with. The defaults do not necessarily work for every situation. I made special rules for all the BGA nets, since those were tighter than what I wanted for the rest of the board.
https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf (https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf)
By the way, KiCAD is simply awesome.
Matthew
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Thanks dnotq, that’s great!
You are right, first I looked at the package, but then I realized my mistake and I looked at the footprint that I downloaded from Snapeda. The pads are 0.45mm.
I found that Xilinx document but I didn’t look at the recommended footprint/ pad size, I looked only at the recommended fanout. :palm:
In the light of your new revelations, I think I can make a 4 layer board with JLC, if I don’t want to route all the I/Os. The reason for JLC is their assembly, I want 0402s and I want them to place them, otherwise PCBWAY is my board house for few years.
What are the DRC rules for the BGA in the attachment? Can you post a screenshot from your board options? I’m just starting with Kicad.
Edit: Is there a way to auto align a via to the four pads around it?
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@knapik the DRC system has been totally reworked in nightly. So please do not confuse users with the new unstable stuff that is currently rabidly changing.
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For reference KiCad version 5 can only define clearances on the netclass, footprint or pad level. All of that is found under file->board setup in KiCad 5.1.6 (the same is true for all 5.1.x releases including future ones, as minor releases are not allowed to change KiCads interface or behaviour)
Sorry, I thought some help would be better than no help.
Edit: Is there a way to auto align a via to the four pads around it?
I'm not sure how it is done in Eagle, but my assumption is no.
Given that its 0.8mm pitch, you can align the BGA on a 1mm grid and then use a 0.2mm grid for via alignment. By pressing Ctrl-T you can create arrays of vias as well (but they won't be assigned a net automatically this way).
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I'm not sure how it is done in Eagle, but my assumption is no.
Given that its 0.8mm pitch, you can align the BGA on a 1mm grid and then use a 0.2mm grid for via alignment. By pressing Ctrl-T you can create arrays of vias as well (but they won't be assigned a net automatically this way).
Yes, that's how I do it in Eagle as well. I can align components but not components to the pads of other components. I learned to play with the grid to my advantage.
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A simple way is to change the grid origin: (Pcbnew / View / Grid Settings).
Because of it's open-source-ness, a lot of side projects have sprung up around KiCad. Pcbnew also has an internal scripting interface, and you can find some scripts around the 'net, most are on github, but some are on external sites only.
An overview of (some of) these scripts is on:
https://github.com/xesscorp/kicad-3rd-party-tools
A script that may be useful to you is:
https://github.com/Laksen/kicad-bga-tools
This script seems to be quite old though, and therefore probably written for an older version of KiCad, so probably it will not run without modifications.
Just Curious:
Why do you use SnapEda libraries?
These sometimes have some compatibility problems with KiCad, while there are already a lot of BGA footprints in KiCad. There are also Footprint wizards in KiCad and you can make new footprints very easily in KiCad (if they fit the wizard format).
Currently there are 13 Footprint wizards in KiCad, and rectangular BGA's is one of them.
Scripts and Footprints Wizards are both written in Python, so if you want similar, but not quite, the behaviour of them, they are relatively easy to adjust.
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Just Curious:
Why do you use SnapEda libraries?
These sometimes have some compatibility problems with KiCad, while there are already a lot of BGA footprints in KiCad. There are also Footprint wizards in KiCad and you can make new footprints very easily in KiCad (if they fit the wizard format).
I don't know, bad (or good) habit from Eagle. I actually like the symbol and footprint in one library but I'm still learning the Kicad way.
One issue I see with the symbol is overlapping pins, see attached. Multiple pins in the same net have their names overlapping. It doesn't happen in Eagle.
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That shouldn't happen. It can be handy to group some pins on the same location, but there's an option in the symbol editor to make certain pins non visible to prevent text overlap. I've never encountered this with the KiCAD component libaries, could just be an error with the snapeda libraries.
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Edit: Is there a way to auto align a via to the four pads around it?
For a 0.8mm pitch device, set the grid to 0.4mm and set the grid origin to pad A1 (or do this before placing the BGA footprint)? Then when you place vias they will be centered between the pads.
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Are there any good Altera/Intel libraries for Kicad? I would like a symbol that has separate blocks rather than one big blob with all the I/Os.
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Today, I downloaded a library from Ultralibrarian. It looks Ok, the symbol is separated in units, but when I checked the pinout, it is all messed up. The part numbers available for download are 5CEFA7U19 and 5CEFA7U19C7N, no matter what I select, the pinout is wrong. For example, nCONFIG pin is A4, in UL symbol it is K5. Am I doing something wrong?
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Today, I downloaded a library from Ultralibrarian. It looks Ok, the symbol is separated in units, but when I checked the pinout, it is all messed up. The part numbers available for download are 5CEFA7U19 and 5CEFA7U19C7N, no matter what I select, the pinout is wrong. For example, nCONFIG pin is A4, in UL symbol it is K5. Am I doing something wrong?
Ask Ultralibrarian.
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On 2020-07-01 I mentioned some scripts and side projects around KiCad.
One of these side projects is to aid in copying pin table text from a datasheet into a spreadsheet, do some post processing, and then generate a KiCad schematic symbol from the spreadsheet.
I have not used this myself because the components I use are all low pin count.
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Ask Ultralibrarian.
I asked and they corrected it. Thanks!
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On 2020-07-01 I mentioned some scripts and side projects around KiCad.
One of these side projects is to aid in copying pin table text from a datasheet into a spreadsheet, do some post processing, and then generate a KiCad schematic symbol from the spreadsheet.
I have not used this myself because the components I use are all low pin count.
Thanks! I’ve seen them but I’m new to Kicad. I’m starting to walk now. Once I start running, I’ll give them a try.
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Ask Ultralibrarian.
I asked and they corrected it. Thanks!
Excellent!