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Label interconnects?

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paulca:
I need a way to interconnect two labels and emit the error about them being connected to the same thing if possible.


I am doing a schematic, the first in a long while.  I'm trying sectionalise it as much as practical.

I have 2 MCUs an ESP32 and a STM32F411.  The ESP32 is just a Wifi module.

Version 1:  Will be for my own purposes and only used pins will be routed and connected.  Interconnects will be straight through as tracks.  A custom SPI header for an ILI9341 TFT screen.
Version 2:  If V1 works.  Will breakout all the GPIO pins on both MCUs and provide jumpers for the "standard" inter-connects, so that they may be disconnected and tapped for other purposes.... thus making the board a generic dev module.  The TFT may, or may not remain.

So in planning ahead I created labels on each MCU, distinct on both sides.  Example:

STM32:WIFI_IC_ENABLE  ----   ESP32:ESP32_ENABLE

Then I show a block of interconnects right in the middle of the schematic.  Later these distinct labels will terminate on a jumper on either side.

KiCAD flags this as an error as they are both on the same wire technically.

Options:
1.  Give up and just make the labels the same and re-label them when the jumpers are added.
2.  Find a way to exclude that specific error and accept the tranlated net names.
3.  Some other way to do the same thing....
4.  Don't bother it just adds complexity, call the spade a spade on both sides!

Thoughts?  Opinion?  Suggestions?

paulca:
Ooops.  PFA draft, work in progress schematic.

 wip_homedashboard.pdf (133.17 kB - downloaded 73 times.)

Benta:
Quite frankly, I hate that way of drawing "schematics", and KiCAD will not support it well.
"Little boxes, little boxes, made of ticky-tacky...", well you get the idea.
What's your problem with wires/connections?

If you want to "sectionalise" it, the solution is hierachical sheets. But that would be a total overkill for a circuit that simple.

julian1:
I would almost be temped to use net-ties to support indpendent nets that are semantically equivalent. Although it's definitely a smell/messy. Normally they are reserved for when one needs to break trace/netclass properties (eg. star gnds, kelvin sensing etc).

Alternatively, use parallel resistor packs, or 0R jumpers.

SiliconWizard:
I don't really get your problem. If you want to use different net names that end up interconnected, use hierarchical sheets, and connect those nets on the higher level. Done.

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