Minimum via size (drill vs. finished hole size)

[homebrew]

Hi everyone

I probably have already figured this out partially but would want to have a second opinion before wasting an entire layout process before finding out that the design is not manufacturable.

* I'm doing a (quite) challenging design with 0.8mm pitch BGAs. Thus I NEED to minimise the via sizes as much as possible.
* I want to order at eurocircuits using their pooling service for an 8 layer impedance controlled board.

Their specs seem to be:
a) 0.1 mm smallest FINISHED hole size
b) 0.1 mm anular ring on outler layers
c) 0.125 mm anular ring on the inside
d) 0.1mm (finished hole size) + 0.1mm (compensation for tool size) smallest drill tool size (makes sense: aspect 1:8 on a standard 1.6mm board)

So as KiCad cannot handle different anular rings on different layers all anular rings must therefore be 0.125 mm. From what I read at their website it seems (and that's exactly where I'm not 100% sure) that the annular ring must be added to the tool-size and NOT to the finished hole size. At least for the inner layers that makes sense to me from the perspective of drill tolerances.

Thus, a via with these manufacturing capabilities and KiCads non-capabilities for complex via designs, results in:

0.1mm (finished hole size) + 0.1mm (compensation for tool size) + 2 * 0.125mm (innere anular ring) = 0.45 mm (minimum via diameter)

Questions:
1) Is 0.45mm the correct minimum diameter given the aforementioned proerties?
2) What do I specify in KiCad? Finished hole size or tool size (thus 0.1mm via drill or 0.2mm via drill)?

[Karel]

Have you already asked here?

https://forum.kicad.info/

The developers of KiCad hang around there too.

[homebrew]

No,I didn't because at least the first part of the question is rather related to conventions of PCB manufacturing to some degree but also dependent on the CAD-tool. Actually, I thought of posting it here in the manufacturing and assembly sections BUT as the questions also depends on the modelling capabilities of KiCad I was hoping to find someone around here that has had the exact same problem/question before.

I was actually surprised that this "simple" piece of information (i.e. what is the minimum via size) is so hard to find/derive.

[Karel]

What I would do if I were you, is to make a very minimalistic project that contains at least some vias and a board edge.
Then export the pcb to gerber and upload it to Eurocircuits. After the analyzing stage, you can check it for manufacturing errors without the need to order it.
Works very well.

[bpiphany]

If variable pad size per layer is not something that has been added to the nightlies, I don't know. There's always the possibility to hack it yourself. Set the via pad size to say 0.45001, to make the via pads easily recognizable. Then you can easily change that aperture in the gerber files for the individual layers. It should just involve changing a single value at the start of the file. Change to 0.4 on outer layers, 0.45 on inner layers. This will mess a little bit with DRC, which you'd have to take into account.

You could also make a via "footprint", but that would likely get annoying really soon. Adding pads of different sizes to each layer. Or incorporate the vias for the BGA breakout directly in the footprint for the part. Lay the board out first, then alter the footprint to have via pads where needed.

Nope that doesn't work. Pad definitions seem to be possible only on F.Cu and B.Cu.

[Karel]

There's always the possibility to hack it yourself.

The blessings of open file formats. 

[langwadt]

if very restricted on routing space https://en.wikipedia.org/wiki/Non_functional_pad is another thing to consider, if the manufacturer is going to remove the internal annular rings that doesn't connect to anything you might as well use the space for routing

[tszaboo]

They have a quite confusing description of IAR and OAR on their website. Altium had also different definition for these things.
So I did this, just for the sake of my mind:
Made a PCB design of a 10x10cm PCB. I placed 100 via on it in a grid, I increased the drill size on the X axis by 0.05mm and increased the pad size on the Y axis by 0.05mm.
Then I generated the gerber and NC-Drill files. Went on their website and uploaded the files.
Their online DRC marked every via that they cannot make. Select one that they can.

[homebrew]

if very restricted on routing space https://en.wikipedia.org/wiki/Non_functional_pad is another thing to consider, if the manufacturer is going to remove the internal annular rings that doesn't connect to anything you might as well use the space for routing

That is a really good idea and as far as their documentation goes, they do support that in general (vias without anular rings on inner layers). However, in KiCad I cannot define this and hence would have to live with thousands of DRC errors. I'm sure that way I would miss the important and true DRC violations.

If it has not already been done, this would probably be worth a feature request at the KiCad project.

[homebrew]

They have a quite confusing description of IAR and OAR on their website. Altium had also different definition for these things.
So I did this, just for the sake of my mind:
Made a PCB design of a 10x10cm PCB. I placed 100 via on it in a grid, I increased the drill size on the X axis by 0.05mm and increased the pad size on the Y axis by 0.05mm.
Then I generated the gerber and NC-Drill files. Went on their website and uploaded the files.
Their online DRC marked every via that they cannot make. Select one that they can.

THAT is an excellent idea - thanks for sharing. I wasn't aware that their DRC checker during the ordering process is that specific.
If validation during the pre-ordering stage is that specific, it would be EXCELLENT!

[tszaboo]

They have a quite confusing description of IAR and OAR on their website. Altium had also different definition for these things.
So I did this, just for the sake of my mind:
Made a PCB design of a 10x10cm PCB. I placed 100 via on it in a grid, I increased the drill size on the X axis by 0.05mm and increased the pad size on the Y axis by 0.05mm.
Then I generated the gerber and NC-Drill files. Went on their website and uploaded the files.
Their online DRC marked every via that they cannot make. Select one that they can.

THAT is an excellent idea - thanks for sharing. I wasn't aware that their DRC checker during the ordering process is that specific.
If validation during the pre-ordering stage is that specific, it would be EXCELLENT!

To be honest, I'm not very happy with their IAR and OAR sizes. It is very large for my liking, and I usually end up with boards that they have to make with their Class 8 technology. Otherwise I just cannot fanout a 0.5mm pitch QFN RF IC properly, or I end up loosing pins because the bypassing and the via for the bypassing blocks them.
Other companies offer that by default, for Eurocircuits it is a price adder.
They are a really nice and professional company to work with, but they should probably buy better drills.