Need help with a NAND gate component simulation

[shapirus]

So after a period of staying away from KiCad for its lack of realtime/interactive simulation I decided to give it another try. I've had success with simulating some basic things, including a 555-based oscillator, for which I had to borrow a model from the OrCAD library, which, fortunately, worked fine with ngspice.

Less luck with a NAND gate, a circuit having which I tried to simulate. I decided to use a generic 4093 for this. There are two models that can be found on the internet, either for CD4093B, or HEF4093B, and there are multiple sources, but the actual models found there seem to be the same.

Neither of them work for me. Both are in the "supported" list in the library that someone has gathered from various sources here: https://github.com/kicad-spice-library/KiCad-Spice-Library/tree/master, which makes me think that the problem isn't in the library, but maybe I am doing something wrong.

Here's ngspice output for the CD4093B model (from cmos.lib):

Code: [Select]

Note: Compatibility modes selected: ps lt a
Circuit: KiCad schematic
Error on line:
a.xu1.auf0 [ probe_int_net-_u1a-vdd__xu1_1 probe_int_net-_u1a-vdd__xu1_2 ] probe_int_nand_out_xu1_3 xu1:d_auf0_nand
MIF-ERROR - unable to find definition of model xu1:d_auf0_nand
Error: circuit not parsed.

And for HEF4093B:

Code: [Select]

Note: Compatibility modes selected: ps lt a
Circuit: KiCad schematic
Netlist line no. 0:
Undefined parameter [rpar]
Netlist line no. 0:
Cannot compute substitute
Please check your input netlist.
Error: ngspice.dll cannot recover and awaits to be detached
Note: can't find the initialization file spinit.

Key message in the latter is "Undefined parameter [rpar]", I believe.

In both cases it appears that KiCad generates output for ngspice that it cannot parse and throws errors in reponse.

How can this be fixed? Any idea what the errors actually mean?

Are there any workarounds? Any substitution models that are known to work? There definitely should be a way to simulate something as basic as a 40 years old NAND gate.

I'm attaching a minimal schematics and the libraries (zipped) that I tried to use.

[shapirus]

Further findings. After removing the "Rpar" parameters from the model's subcircuit there's now a different error:

Code: [Select]

Note: Compatibility modes selected: ps lt a
Circuit: KiCad schematic
Error: no such function 'tbl'
Error: no such function 'tbl'
Error: no such function 'tbl'
Error: no such function 'tbl'
Error: no such function 'tbl'
Error on line:
b.xu1.bha xu1.ha probe_int_probe_int_nc-u1-1_xu1_5_xu1_5 v= ( ternary_fcn ( ( ( v(probe_int_probe_int_net-_u1a-vdd__xu1_1_xu1_1,probe_int_probe_int_nc-u1-1_xu1_5_xu1_5) > tbl ( v(probe_int_probe_int_nc-u1-0_xu1_4_xu1_4,probe_int_probe_int_nc-u1-1_xu1_5_xu1_5) ,   0.0000000000e+00 ,   0.0000000000e+00 ,   3.3000000000e+00 ,   1.7000000000e+00 ,   5.0000000000e+00 ,   3.0000000000e+00 ,   1.0000000000e+01 ,   5.8000000000e+00 ,   1.5000000000e+01 ,   8.3000000000e+00 ) ) ) ,   0.0000000000e+00 , ( v(probe_int_probe_int_nc-u1-0_xu1_4_xu1_4,probe_int_probe_int_nc-u1-1_xu1_5_xu1_5) ) ) )
parameter value out of range or the wrong type
Error: circuit not parsed.

Clearly, ngspice failed before because it did not recognize the "rpar" parameter, and now it fails because it does not recognize the "tbl" function which is specific to some other spice dialect (LTSpice?)

Example:

Code: [Select]

bha ha vss v=if((v(a,vss)> tbl(v(vdd,vss),0,0,3.3,1.7,5,3,10,5.8,15,8.3) ),0,v(vdd,vss))

It can probably be rewritten in a way that ngspice will understand, but... Am I the first user of ngspice on this planet who tries to use a 4093 IC in an ngspice simulation?! How do others solve this?

Update: so yes, this is LTSpice syntax and functionality that ngspice doesn't recognize and implement even in the LTSpice compatibility mode. From what I could find so far, it doesn't have a concept of interpolated lookup tables like in the above expression, and it can be, to an extent, rewritten with a sequence of ternary operators. Can someone confirm this? Is there an easier way?

[shapirus]

...another update.

Okay, another model, finally, seems to work, after assigning the pins properly. It's the PSPICE model downloadable from the TI website at https://www.ti.com/product/CD4093B#design-development.

TI models are generally rather good, and they used to be available packaged in a single zip archive, but now that archive doesn't contain any files (only directories), which is a bummer. I wonder if anyone has it saved and can share.

[Benta]

What's compatibility mode "a"?
Haven't seen that before.

[SiliconWizard]

https://ngspice.sourceforge.io/docs/ngspice-html-manual/manual.xhtml#magicparlabel-23836

[Benta]

Ah.
Thanks, I hadn't seen it in any of my own simulations.

[shapirus]

btw, for the logic ICs, the 7400 series (TI models again) mostly seem to work and there are many models, unlike the 4000 series. They also don't care much, it seems, about supply and input voltages, so they can be used to simulate the same gates of other chip series. It's often tricky to make the simulation work without getting "timestep too small", but I have found that it often happens at fast state transitions when, apparently, ngspice runs into an infinite current condition or something like that. Adding a small series parasitic resistance with the respective input or component (ideally in the model, to prevent it from making its way onto the PCB) often helps.

Speaking of parasitics, btw, does anyone know of a way to universally add a series parasitic resistance to every component in ngspice? There are parameters for parallel parasitics (cshunt and rshunt), which work fine, and "rseries", which I didn't try, but the manual says that rseries only works for inductors.