Seems silly to not treat an inductor like a wire, but at least it makes some sense.There is no way for it to know that this is an inductor, it is just a component with two passive pins. To implement that check, components would need to have additional attributes for ERC use.
Wouldn't it be able to derive the device type from the symbol?How? It is just 2 pins and 4 semicircles. It has no idea on what this represents. There is no way to specify that it is a short for ERC use.
// We examine only a given net. We stop the search if the net changes
if( ( netItemTst >= aList->size() ) // End of list
|| ( aList->GetItemNet( aNetItemRef ) !=
aList->GetItemNet( netItemTst ) ) ) // End of netI think a good compromise would be if the net had a power port connector, even if there is no other corresponding power ports anywhere else. So put a power symbol named "VDDCORE", and ERC takes it as a sign that the pin is powered.
I'm not even sure, this may actually work.
I think that's effectively what PWR_FLAG does, so the ERC throws a warning saying 'hey this might not be connected' then you slap in the new symbol to confirm you looked at it and traced the net to confirm it is indeed connected.Yes, that's it. I think it is a good solution. This clearly conveys the designer's intent.
100uF also seeems a bit big,Yeah, they should probably be 100nF, not 100µF. Looks like basic supply decoupling. Just a single 100µF cap on a supply pin - or multiple supply pins - makes little sense...
I am more used to putting capacitors upright so the electrons don't fall out and having power flow downwards into a chip..https://www.eevblog.com/forum/index.php?action=dlattach;topic=168629.0;attach=651450;image (https://www.eevblog.com/forum/index.php?action=dlattach;topic=168629.0;attach=651450;image)
I also combine this with giving the PWR_FLAG's a logical place in the schematic.
This makes them look like they belong there, instead of being slapped on as an afterthought.
That's also the reason I put them on the same level as the +3.3V power supply symbol.
At least to me this makes the intention a lot clearer, but I'm biased here because I'm used to my own way of drawing things.
I also have a suspicion that Pin 8 "VDDana" is missing a decoupling cap.
100uF also seeems a bit big, ceramics are more common, but I don't know what chip you're using so can't comment too much about that
Thanks for the tips, that does look a lot more eye pleasing.