TI's TPS7A701x symbol and ERC.

[Jonathon_Doran]

This is a voltage regulator IC.  There are two output pins with the same name "OUT".  This is per the datasheet.  Pins 1, 20 I assume are connected together.  I expect them to be on the same net.  The symbol came from TI, and I figure they know what they are doing.  The datasheet comes from TI, and I figure they know what they are doing here as well.

But KiCad fails the ERC saying that two power outputs are connected together.  Yes, I think that is how the chip is designed.

Pin 20 is hidden.  I cannot connect a wire to it.  I do not want to.  But KiCad is still upset about the two power outputs.

I'm sure someone out there has experience with something like this.  Please advise me.

I hate to ignore ERC errors.

[ataradov]

OUT is already a power output, you don't need a power flag.

[Doctorandus_P]

The ERC system is a single / simple minded system. It just follows simple rules and one of those rules is that it generates an error if two power output pins are connected together.

If you use pin stacking, (putting multiple pins at the same location, and hiding all except one) then it's recommended in the KiCad manual to set all the hidden pins to pin type "passive".

[ataradov]

Stacking power pins of the same net is fine. In this case there are two errors - one for each pin conflicting with the power flag. There is no mutual conflict between the pins themselves.

[Doctorandus_P]

Stacking power pins of the same net is fine.

No, it's not. As I already wrote, Two output pins connected together generate an ERC violation. It is just that simple.

It's a bit obscured in the screenshots, but this symbol has pins 1 (seen in the schematic) and pin 20 (shown in the ERC window) and that does not work in KiCad.

For another example, you can look at the RT9071 from KiCad's default libraries. It shows pin 1 as a visible power output, and pin 5 as a hidden stacked pin and that one is set to passive.

In this case there are two errors - one for each pin conflicting with the power flag.

Yes, there are two errors, but only the second is for the power flag (Conflict between the power flag #FLG5 and U2 pin 1)
The first error is for the hidden power output pin of U2. (The other presumably pin 1 of the same symbol).

Unfortunately it's obsured by the "click on items to highlight them on the board" message what the first item is.
But no matter what the message is. It is a total of three "power outputs" connected together, while only one is allowed.

Aditionally, It's literally stated in the KLC:
Connecting Output or Power Output pins would result in an ERC error. Output pins that always need to be connected together must therefore be stacked. The invisible pins get the pin type passive in this case.


https://klc.kicad.org/symbol/s4/s4.3/

[ataradov]

I can't reproduce this. I use stacked power pins a lot and never seen any ERC warnings about that.

[Doctorandus_P]

As it turns out, TPS7A4701xRGW is a symbol from KiCad's default libraries, so I re-created the project.

GND needs a PWR_FLG, because it's a power input.

The output pin may not have a PWR_FLAG because it already is a Power out (actually 2 power outputs).
Without the PWR_FLAG on pin 1 I get no ERC violations.
With a PWR_FLAG on on pin 1 I get two ERC violations, and as Ataradov has said, both are indeed for the PWR_FLAG and each of the Power output pins of the symbol.



So now I am confused because this contradicts both with my previous experiences and with the KLC.
I also added the test project.
 asdf_power_output.zip (6.8 kB - downloaded 24 times.)

[exmadscientist]

As an aside, it is generally considered an extremely bad idea to hide active pins like pin 20 here from your schematic symbol.

Think about what happens when you get your board back, or years down the line when you're trying to repurpose one of these for something else. It isn't doing what you want and you're probing it, as one does. You're looking at the schematic... and wondering why this weird pin 20 has voltage on it. What's broken? Is anything broken?

You could say that you have to have the datasheet open. Have you seen how many ICs are on a normal board these days? That's not a reasonable approach. Please, just show all active pins on the symbol. Things get much easier to debug, analyze, and fix that way. And the price is one pin on your schematic, which is pretty low!

(Many engineers insist that you mustn't hide any pins from a symbol, even NC pins. I don't go that far; I think no-connects are more clutter than use to show, and am pretty comfortable with the convention "any pin not shown is expected to be dead". But I see their point. I also don't do aerospace or class 3 medical work, so that opinion comes with no warranties or regulatory guarantees....)

[Jonathon_Doran]

Thanks everyone, I'll look into editing the symbol.  As was stated, this was from the default library (I misspoke in my earlier message), so it came that way.
I agree that I don't like hiding pins, because what am I supposed to do during layout. 

I was thinking of contacting TI about this earlier.  One option is to connect the two pins physically.  Was the duplication to allow higher current through the part?
I'll try to make the traces extra wide (even though I'm drawing very little current).  Come to think of it I need to add an LED, possibly two.

[SiliconWizard]

I don't like stacked pins either, but it seems like a "standard" practice with most KiCad symbols. I don't recommend it as it hides the pinout, is confusing to read for reviews.

As to ERC, yes, this is a common issue. Some parts have multiple power out pins like this one, that are meant to be on the same net. Unfortunately, I don't think there's anything in KiCad that can let you flag these "grouped" pins appropriately in the Symbol editor, in order to avoid getting this ERC error. So one option to avoid the error is just to mark one of these pins as 'power out', and the others as passive. Not ideal.

[ataradov]

There is no issue with stacking the pins as far as ERC goes. There is no need to mark anything. They all can be power.

I stopped using stacked pins for new symbols, but for the old symbols I did what Eagle used to do. Instead of naming the pin "VDDIO", I would name it "VDDIO*3" if there are actually 3 pins. It still would only show one index, of course, but it is still a reminder that there is more than one physical pin.

Using full version takes up a lot of space, especially for things like FPGAs, but it is not a big deal in a grand scheme of things. Especially that there are unlimited number of sheets, unlike for a free version of Eagle.

[Doctorandus_P]

In general, I do not like stacked pins either. When I'm probing pins on the actual PCB, I also want to be able to find them in the schematic, and thus my opinion does not coincide with the recommendation in the KLC. Pin stacking does make more sense for bigger BGA's. First, then can have 100+ power pins, and those are not even visible on the PCB for probing.

And then,  there are also SMT mosfet's which have several paralleled pins, and showing 8 pins on a schematic for a 3-pin device is also a bit bonkers to me. For such MOSfets, I tend to modify the footprint so it uses only 3 pad numbers. In KiCad, when different pads have the same pad number, you have to connect all of them on the PCB for DRC to be happy. And for such FET's it's usually easy to see on the PCB that pins are paralleled. Pad numbers are also not only numbers, but 4 character alphanumeric strings. This is needed for BGA's and such with "chessboard coordinates" For a MOSfet in an 8-pad footprint you could name the pins "G", "S", and "D".

I guess the best approach is to do it neatly, but accept that perfectionism is not attainable, and attempting to achieve it is a huge time sink for little additonal benefit, so don't overdo it.

[Jonathon_Doran]

I made a copy of the symbol, edited it, and marked the second pin as passive.  It passes the ERC.

I also found a schematic on TI's site that connected the two power pins together, so I'm taking that as direction to do that on the final board when I route.

[ataradov]

I made a copy of the symbol, edited it, and marked the second pin as passive.  It passes the ERC.

It should have passed ERC as is if you remove redundant power flag. Did you actually have an error without the flag? If so, what version if KiCad are you using?

[Warhawk]

Please note that the datasheet recommends 10uF for C_in and 1uF for C_nr. You have picofarads instead. 1pF is a very esoteric capacitance applicable maybe in RF circuitry.