I did an experiment and made a board for JLCPCB with 0.2/0.35 vias. And wow, boy did that make layout MUCH easier than with my normal 0.3/0.45 vias. It's pricier though; ~$14.50 for the 0.2mm drill size and ~16.50 for 4-lead Kelvin testing which they strongly recommend for 0.2/(0.30,0.35) or smaller vias. (It can be skipped, probably after signing a waiver in blood.

) Although they allow 3.5/3.5 w/s traces I didn't do anything finer than 5/4, just getting the via size down made a HUGE difference.
However, KiCad complained on every single 0.2/0.35 via, that the 0.125mm annular is smaller than the minimum set limit of 0.13 (which I pulled off their site). It's not complaining for 0.3/0.45. Where does this come from? Is it derating it for plating, while JLCPCB's spec includes plating & plugging? My math says 0.15mm annular in both cases. Is there something else impacting this that I'm missing? I see no other relevant settings, beyond min hole size (0.2mm), minimim via size (0.35mm) and min annular (0.13). Drill precision? Something else?
They accepted my files without comment, I'm sure if my vias were bad (there's like 100 of them, not easily just enlarged) they'd tell me to fix it. One or two with 0.125 vs 0.13 might be waived through, but not 100 if they're actually pushing the envelope.