Author Topic: Via annular too small (0.125 vs 0.13 limit)  (Read 1547 times)

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Offline bsonTopic starter

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Via annular too small (0.125 vs 0.13 limit)
« on: October 08, 2024, 09:31:54 pm »
I did an experiment and made a board for JLCPCB with 0.2/0.35 vias.  And wow, boy did that make layout MUCH easier than with my normal 0.3/0.45 vias. It's pricier though; ~$14.50 for the 0.2mm drill size and ~16.50 for 4-lead Kelvin testing which they strongly recommend for 0.2/(0.30,0.35) or smaller vias.  (It can be skipped, probably after signing a waiver in blood. :))  Although they allow 3.5/3.5 w/s traces I didn't do anything finer than 5/4, just getting the via size down made a HUGE difference.

However, KiCad complained on every single 0.2/0.35 via, that the 0.125mm annular is smaller than the minimum set limit of 0.13 (which I pulled off their site).  It's not complaining for 0.3/0.45.  Where does this come from?  Is it derating it for plating, while JLCPCB's spec includes plating & plugging?  My math says 0.15mm annular in both cases.  Is there something else impacting this that I'm missing?  I see no other relevant settings, beyond min hole size (0.2mm), minimim via size (0.35mm) and min annular (0.13).  Drill precision?  Something else?

They accepted my files without comment, I'm sure if my vias were bad (there's like 100 of them, not easily just enlarged) they'd tell me to fix it.  One or two with 0.125 vs 0.13 might be waived through, but not 100 if they're actually pushing the envelope.
« Last Edit: October 08, 2024, 09:34:45 pm by bson »
 

Offline Doctorandus_P

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Re: Via annular too small (0.125 vs 0.13 limit)
« Reply #1 on: October 08, 2024, 11:24:34 pm »
For KiCad, it is just some numbers that you can set in PCB Editor / File / Board Setup / Design Rules / Constraints KiCad is happy to draw tracks and holes down to nano meter sizes, and you have to decide for yourself what are sensible limits that both you and your PCB manufacturer can work with.
« Last Edit: October 09, 2024, 12:26:40 am by Doctorandus_P »
 

Online SiliconWizard

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Re: Via annular too small (0.125 vs 0.13 limit)
« Reply #2 on: October 08, 2024, 11:50:28 pm »
For KiCad, it is just some numbers that you can set in PCB Editor / File / Board Setup / Design Rules / Constants KiCad is happy to draw tracks and holes down to nano meter sizes, and you have to decide for yourself what are sensible limits that both you and your PCB manufacturer can work with.

But question was, what numbers exactly, as it was not clear to bson why KiCad would consider that the annular ring for a 0.2/0.35 via is 0.125 - and it's not really for me either?
Yes, unless it's a bug, KiCad probably has some settings (that the user can change, or not?) for defining tolerance for vias, but where is it?
« Last Edit: October 08, 2024, 11:53:26 pm by SiliconWizard »
 

Offline ebastler

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Re: Via annular too small (0.125 vs 0.13 limit)
« Reply #3 on: October 09, 2024, 05:16:56 pm »
However, KiCad complained on every single 0.2/0.35 via, that the 0.125mm annular is smaller than the minimum set limit of 0.13 (which I pulled off their site).  It's not complaining for 0.3/0.45.  Where does this come from?  Is it derating it for plating, while JLCPCB's spec includes plating & plugging?  My math says 0.15mm annular in both cases.  Is there something else impacting this that I'm missing?  I see no other relevant settings, beyond min hole size (0.2mm), minimim via size (0.35mm) and min annular (0.13).  Drill precision?  Something else?

Umm... in my book the the annular ring width is half of (via size - hole size). So for 0.35 mm via diameter and 0.2 mm drill diameter, the ring would be (0.35 - 0.2) / 2 mm = 0.075 mm wide.

Where did you find the 0.13 mm minimum annular width on the JLCPCB site? That does not align at all with the via drill and diameter specs you quoted.
 

Online SiliconWizard

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Re: Via annular too small (0.125 vs 0.13 limit)
« Reply #4 on: October 09, 2024, 08:10:52 pm »
But the weird part is that KiCad doesn't seem to warn about 0.3/0.45 vias, which should have the same annular ring width? So, I'm personally not sure about what KiCad does here, but maybe this is obvious and I missed it.

Otherwise, you're right, I also wonder where the OP found this 0.13mm value. This is what JLCPCB specifies for vias:

Quote
1-layer (NPTH only): 0.3 mm hole size / 0.5 mm via diameter
2-layer: 0.15mm hole size / 0.25mm via diameter
Multilayer: 0.15 mm hole size / 0.25 mm via diameter

① Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size.
② Preferred Min. Via hole size: 0.2mm
 

Offline bsonTopic starter

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Re: Via annular too small (0.125 vs 0.13 limit)
« Reply #5 on: October 11, 2024, 05:01:22 am »
Oh yeah, it should be 0.15mm.  And it's not even the annular, it's the via size over the hole.  Which makes it even more mysterious why KiCad would complain.

So while I should have specified a 0.075 minimum annular, that doesn't really explain where the 0.125 came from.  :-//
« Last Edit: October 11, 2024, 05:14:13 am by bson »
 

Online SiliconWizard

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Re: Via annular too small (0.125 vs 0.13 limit)
« Reply #6 on: October 11, 2024, 08:44:20 am »
Yes, I don't understand it either. But you could definitely ask on https://forum.kicad.info/ - there's decent activity there.

Note though that as we said, not sure where you got this 0.13mm min value from. JLCPCB capabilities as far as vias go are as I quoted above. (Which is pretty "generous" for a low-cost fab IMO. But I think they may have improved their capabilities relatively "recently", as I remember that they didn't allow such small vias in the past.)

But regarding regular PTH, they require a min annular ring of 0.20mm. So that your constraint of 0.13mm is like optimistic. They say 0.15mm absolute min for 4+ layer PCBs, but still recommend 0.20mm min.
Which yes, means that they accept narrower annular rings for vias.

But now that you raise the point, I'm not sure how KiCad handles it exactly. My default constraint for 4-layer PCB for JLCPCB is 0.15mm for annular rings. I routinely use 0.3/0.45 vias and KiCad never complains.
 

Offline bsonTopic starter

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Re: Via annular too small (0.125 vs 0.13 limit)
« Reply #7 on: October 11, 2024, 11:58:37 pm »
The complaint is actually that it's less than the minimum for the netclass.  (Which I presume is the value set for the netclass, even though it doesn't explicitly spell out that it's a minimum.)

But the value shown was not that of the netclass but the absolute minimum...
 


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