Author Topic: Clearance violations for copper on same net  (Read 1861 times)

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Offline SiliconWizardTopic starter

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Clearance violations for copper on same net
« on: November 21, 2022, 04:04:37 am »
This one is driving me nuts. I get clearance violations when I add copper (lines/polygons...) on the same net to get more copper than single tracks. How do you get around this? I'm sure this is possible as people regularly advise doing this to enlarge connections, manually create teardrops, etc.

I'm sure I'm missing something. What is it?
 

Online tautech

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Re: Clearance violations for copper on same net
« Reply #1 on: November 21, 2022, 05:22:32 am »
Been caught with similar in Altium and it's normally improper trace snap connections, that is each section of the trace doesn't connect perfectly to another section.

Delete the Net and lay it out again or if there are only a few changes in the trace inspect them very carefully.
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Offline SiliconWizardTopic starter

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Re: Clearance violations for copper on same net
« Reply #2 on: November 21, 2022, 07:52:42 pm »
OK I found the culprit. Two issues actually.

- Probably obvious for KiCad aficionados: any copper that you manually add should be assigned the same net. So if you want to add copper, you basically have to create zones AND assign them the same net. Do not let the net unassigned, otherwise KiCad will not be "clever" enough to detect a connection on the same net, it will treat the added zone as "orphaned" copper and this will be a violation even if there is no electrical issue whatsoever. This kinda makes sense though, as there could be unwanted orphaned copper. But I think the violation message could in this case be a bit more specific.

Also, do not use graphic shapes for this, only use filled zones, because I don't think you can assign a net to a graphic shape, only to filled zones. If anyone knows better about this point, please let us know.

- The other issue was in a footprint that also had graphic shapes on top of some pads. I had to correct it. But as opposed to the layout editor (unless again I missed something), the footprint editor can allow you to combine several graphic shapes into a single pad, which is pretty handy. (Right click / Edit pad as graphic shapes) So I merged all added graphics shapes this way and the violations went away.
 

Online tautech

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Re: Clearance violations for copper on same net
« Reply #3 on: November 21, 2022, 08:02:17 pm »
OK I found the culprit. Two issues actually.

- Probably obvious for KiCad aficionados: any copper that you manually add should be assigned the same net. So if you want to add copper, you basically have to create zones AND assign them the same net. Do not let the net unassigned, otherwise KiCad will not be "clever" enough to detect a connection on the same net, it will treat the added zone as "orphaned" copper and this will be a violation even if there is no electrical issue whatsoever. This kinda makes sense though, as there could be unwanted orphaned copper. But I think the violation message could in this case be a bit more specific.
Yep, Altium dos that too. When you magnify enough you should be able to see the Net labeling that if not all the same is the reason why you get a violation.

As you use PCB CAD's more sorting all this stuff becomes somewhat 2nd nature.
Enjoy the journey.  :)

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Offline JeffYoung

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Re: Clearance violations for copper on same net
« Reply #4 on: January 14, 2023, 10:45:01 pm »
Correct: KiCad does not at present support nets for graphic objects, only zones.  It is in the feature-request list though....
 


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