why is KiCAD not following rules for nets. VDD turns into GND

[coppercone2]

I have a schematic I made. I have nets. Like VDD, VSS and GND.

On the schematic they look fine. On the PCB editor the nets are renamed. Like VDD does not wanna exist and I get caps with GND on both sides.

How do I just make it plot what the hell is in the schematic without making decisions to change something based on something I can't find. I don't need that feature. I figure its some crap with the parts. I just want it to do what it says its doing.

I don't want whatever its doing.

I can just plot lines everywhere to make it a star ground on the schematic and then put a plane over it.. but WTF, I should be able to use nets. Why the fuck is it changing the god damn net. There is no problem.

Oh, ok. I wrote this out and then I figured its trying to help me, cryptically. There was a short through a diode on the ass end corner of a schematic bridging things. I guess it would be nice if it told you plausible short circuit. Maybe it does in the ERC but I Have like 999 problems there. The sky is falling because of some floating N/C pin but the short circuit between VDD and GND is hidden on priority #485

[Shonky]

Yep I expected schematic to be wrong when I started reading.

And it would have been a short that you created in your schematic. Who put it in the ass end corner of the schematic?

If you have a heap of problems in DRC then there's your problem. You should have zero. Then it's simple to find real errors like you were having rather than the ones you just want to ignore.

[coppercone2]

maybe if I was being paid to make it at work I am not gonna go through all that BS, not for this prototype, I wanna get this done !!!

i usually proofread it by looking at the print out traces with the data sheets and a marker

[fourfathom]

DRC won't catch this type of error,  but if you did an ERC on the schematic it would have plainly told you "Warning: Both VDD and GND are attached to the same items; VDD will be used in the netlist"
I don't always get to zero "errors", but I do check all the reports to see if they matter.
 

[coppercone2]

need assistant to read this 

i decided to buy good interconnects and make a smaller pcb that i can hook into a different pCB later to test stuff because the mega boards are not worth it until you have zero uncertainty.

i have more options for characterizing the board this way too, I Can know more about it, then making assumptions about the signals


also I am going to put some AC tvs diodes into small pomona boxes that i can hook up to any bnc connector to protect the input like a connector saver so their universal for prototypes, easy to test the effect of, and not have to rework a pcb with expensive parts on it with solder

[Kleinstein]

There may be a possible direct like in the schematics, likely unintentional.

A possibly trouble can be parts with hidden / implicite supply pins. This is common with the single gate logic chips. These parts imply the there supply is GND and VCC even if intended to be used differently.

[JPortici]

Maybe it does in the ERC but I Have like 999 problems there. The sky is falling because of some floating N/C pin but the short circuit between VDD and GND is hidden on priority #485

and maybe 998 of them are "pin X is unconnected", which you can exclude from DRC if you prefer

[Uky]

..Perhaps... KiCAD development team could consider adding the possibility of placing a "Dangle"-marker on intentionally unconnected pins. Thus, excluding this check can be avoided.

 

[3roomlab]

i think i remember seeing the discussion that KICAD no longer uses netlist?
i was not following that progression closely, maybe someone else heard about it and knows more ?
https://forum.kicad.info/t/kicad-7-netlist-doesnt-work-as-supposed-to/41206

[JPortici]

..Perhaps... KiCAD development team could consider adding the possibility of placing a "Dangle"-marker on intentionally unconnected pins. Thus, excluding this check can be avoided.

 

there is already (the "x" symbol that marks the pin as "unconnected")

[Benta]

Instead of whining, why don't you post the project (or at least the schematic)?
Your descriptions are not useful, as you don't quite seem to know what you are doing.

[coppercone2]

pcb does not exist anymore, the socket I got is chirstmas tree, so its gonna be point to point with some braid. two tiny boards. better anyway since I can test some very different packages there

[janoc]

i think i remember seeing the discussion that KICAD no longer uses netlist?
i was not following that progression closely, maybe someone else heard about it and knows more ?
https://forum.kicad.info/t/kicad-7-netlist-doesnt-work-as-supposed-to/41206

It still does, of course. Just you don't need to create it explicitly as a file anymore as it was in the old KiCAD, the netlist gets transferred between the programs in memory.

That dude in the post is doing who knows what given the mismatched symbols and what not he had there, not following the correct workflow - then no wonder that things break for him. Garbage in, garbage out. There was nothing wrong with KiCAD there.

[janoc]

..Perhaps... KiCAD development team could consider adding the possibility of placing a "Dangle"-marker on intentionally unconnected pins. Thus, excluding this check can be avoided.

 

there is already (the "x" symbol that marks the pin as "unconnected")

Yep, just press "Q" on the pin to mark it as unconnected (or use the menu/toolbar). That feature exists since ages ago.

[Doctorandus_P]

I am not gonna go through all that BS, not for this prototype, I wanna get this done !!!

KiCad used to be quite simple minded and easy to use, but over the last few years ever more "advanced" features have been added, and more are comming. (There are over 500 feature requests on gitlab).
And most features are not very difficult to learn, I find KiCad quite straightforward, but I've been using it for 8+ years (although i have not made very many PCB's with it) and my knowledge of KiCad grew gradually with the program itself.

And both ERC and DRC are there to help you. KiCad V7 has gotten a lot more checks, and not all checks are useful for everybody. It is however easy to exclude individual warnings/errors, or whole classes of warnings/errors by right clicking on them in the ERC or DRC dialogs. (The excluded violations can also be easily undone)

i usually proofread it by looking at the print out traces with the data sheets and a marker

Mistakes like shorting a diode though it's body with a wire are easy to make and hard to spot. A good tool for checking netlist connectivity in the schematic is to use the highlight function, which is (by default) under the backtick key (upper left corner of the keyboard on US layout, just under [ESC].)

Rushing a project though KiCad without spending some time on learning KiCad itself does not sound like a good idea to me. There are so many nice things in  KiCad that spending some time to learn them (such as for example the "No Connect Flags" already mentioned) helps boosting your productivity to get things done more effectively.

[coppercone2]

this board was unusually changed alot because I used it kind of like a virtual white board so alot of parts and sections were moved around for 40+ hours and parts added/replaced, something to hit by a stray 'group move' and embedded a strand of wire.

IMO its as good as altiums junior program (circuit studio), which was wayyyyy better then eagle cad (ptsd flashbacks occur with eaglecad). Nothing like someone telling you not to worry about the phantom grid artifact that won't go away because their scared the license won't transfer over. And I swear that eagle changed via layer connections on me before. Ahh so you are paying me ignore the translucent criss cross artifact on my screen that looks like you went out of bounds in ghost mode on a video game. 


first time i saw circuit studio I thought wow you can take some guys off the blood pressure meds if you buy this. kicad is similarly good.

[SiliconWizard]

Just a tip, don't ignore ERC. Not generally a good idea. If you get a lot of warnings or errors, try to understand where they come from and fix that. (Often a single "fix" can solve a lot of warnings all at once.)

[Benta]

Just a tip, don't ignore ERC. Not generally a good idea. If you get a lot of warnings or errors, try to understand where they come from and fix that. (Often a single "fix" can solve a lot of warnings all at once.)

Best advice yet. Listen to it.

[coppercone2]

Idk how you guys stand erc complaints if you did this for money before. I learned to hate cad

If I had some kinda machine to do it manually like a engraver shrink mill router thing I would use it based on hand drawings lol

[Shonky]

And then you'll waste a lot of time trying work out why your boards don't work.

ERC/DRC exists for a reason.

[PlainName]

Idk how you guys stand erc complaints if you did this for money before.

ERC and DRC are like compiler warnings in software - the ideal is to get a clean build with no warnings. When I do this - for money or fun - that's exactly what I intend to end up with, because getting any at tells me there is a potential problem that will probably bite me at the worst time. And, of course, if you get a long list of warnings you mentally ignore, you'll probably never notice the extra one that's Bad News, so a clean slate is important just from that aspect.

As with software, if you know what you're doing and why you're getting the various warnings, you might elect to disable specific ones, or specific instances. But the fewer such exclusions the better the quality of the job is likely to be.

[coppercone2]

when you run DRC in kicad

[bpiphany]

Appropriate response?

[JPortici]

I could write a long list of complaints in kicad.
the two things bugging me the most at the moment are
-different default shortcuts for the same thing in eeschema and pcbnew
-shortcuts i can't change or remove ("S" is giving me the most headaches)

i agree that "nets that overlap each other for whatever reason get merged" is annoying but it's far from being a dealbreaker, that is an user error anyway, so it's far down in my list of complaints.
one thing i'm not going to add to the complaint list is ERC/DRC being overzealous. I do this for money, i also do programming for money and first thing i do is enable every possible warning and setup static analysis. not using check tools because they give too many errors/warning is ridiculous. They can be bogus errors/warnings so you can exclude those checks, but it must be a manual operation.

[janoc]

when you run DRC in kicad
...

Maybe that simply means you are doing something wrong that you have so many errors/warnings? 

In that case KiCAD is actually trying to save your bacon (and wallet) because if your order stuff with errors in it, it is likely to not work or not be manufacturable (or both).

If you really think you know what you are doing (you aren't making a strong case for that here, though ...), you have always the option to turn both the individual diagnostics and also overall ERC/DRC checking off. It is right there in the menu. It is not like anyone is forcing you to use it.

So I am not quite sure what are you whining about? That it can't read minds? When it doesn't warn you about your mistake (because you ignored/disabled the warnings), it is bad KiCAD's fault because it joined two nets you have managed to short together.  And when it does warn you, it is bad KiCAD  again because there are too many warnings that you couldn't be bothered to deal with in your messy schematic?

Hard to satisfy this one ... Maybe you would do better hiring someone who actually knows how to use the software properly to do the job for you?