6 Layer PCB...General structure?

[Faringdon]

Hi,
With a 6 layer PCB, would you agree, that generally the following regime is optimum…..

you have a top layer for components.
Then one layer for ground
One layer for power.
Then one layer for inner layer tracks  running in direction “A”.
Then one layer  for inner layer tracks running in a direction at 90 degrees to “A”.

Then a spare layer, likely the bottom layer, which you can make another ground.

[Siwastaja]

It can work that way but usually, layers are considered as pairs where each other is reference level (ground plane or Vcc plane well decoupled to ground) and the nearby layer is a signal layer. This way, each signal automagically has a return path in the nearby reference plane.

In your system, your "spare layer" which you make a ground works as a pair with the 90degA layer, and the A layer works as a pair with your power plane. So the above description is kind of satisfied, because in typical stackup, the distance between your two signal layers is larger.

Just your terminology makes me wonder this happened by luck. Now if A and A90deg layers were close together with thin prepreg separating them, these signal would couple together, which you would of course minimize by running them 90 degrees in different directions, but still, you can avoid the coupling completely by having every other layer as reference plane.

[alexaraujo]

Hi,
With a 6 layer PCB, would you agree, that generally the following regime is optimum…..

you have a top layer for components.
Then one layer for ground
One layer for power.
Then one layer for inner layer tracks  running in direction “A”.
Then one layer  for inner layer tracks running in a direction at 90 degrees to “A”.

Then a spare layer, likely the bottom layer, which you can make another ground.

.

About Stackup I use some concepts taken from this video with Robert Feranec and Rick Hartley below but also from a document I keep since college.



Hope this helps.

[Feynman]

Yeah, just search for Rick Hartley on youtube. There are several videos with him talking about good and bad 6-layer stack-ups.

[alexaraujo]

I use model 4 as shown in the table below.

I hope it helped you

[McBryce]

There are so many factors that decide the layer assignment. There is no "one size fits all" solution. It depends on how many rails you have, the frequencies you are dealing with, your thermal management solution, the EMC requirements, the current requirements, the component types used...
Anyone who tells you "This is the best method" hasn't understood the problem.

In the many commercial products I've been involved with over the years, the layer assignments were decided after all other factors had been defined.

Bryce.

[asmi]

Here is a stackup I've used for many of my high-speed boards. The PCB is 1.2 mm thick. Boards were manufactured by WellPCB.

Code: [Select]

File names for layers:
------------------------------------------------------------
1:Top.art - 0.035 mm
------------------------------------------------------------
PP - 0.15 mm (~2x1080H)
------------------------------------------------------------
2:GND.art - 0.035 mm |
------------------------|
Fr4 core - 0.13 mm | 0.2 mm FR4 core with 1/1 Oz
------------------------|
3:SIG1.art - 0.035 mm |
------------------------------------------------------------
PP - 0.37 mm (~2x7628H)
------------------------------------------------------------
4:SIG2.art - 0.035 mm |
------------------------|
Fr4 core - 0.13 mm | 0.2 mm FR4 core with 1/1 Oz
------------------------|
5:POWER.art - 0.035 mm |
------------------------------------------------------------
PP - 0.15 mm (~2x1080H)
------------------------------------------------------------
6:BOTTOM.art - 0.035 mm
------------------------------------------------------------

Controlled impedance traces:
---------------------------------------------------------------------------------------------------------
| Layer | Reference plane | Single-ended 50 Ohm width | Differential 100 Ohm width/spacing |
|-------|-----------------------|-------------------------------|---------------------------------------|
| 1 | 2 | 0.2273 mm | 0.1988 mm/0.4 mm |
|-------|-----------------------|-------------------------------|---------------------------------------|
| 3 | 2 | 0.1363 mm | 0.1214 mm/0.4 mm |
|-------|-----------------------|-------------------------------|---------------------------------------|
| 4 | 5 | 0.1363 mm | 0.1214 mm/0.4 mm |
|-------|-----------------------|-------------------------------|---------------------------------------|
| 6 | 5 | 0.2273 mm | 0.1988 mm/0.4 mm |
---------------------------------------------------------------------------------------------------------


[EE-digger]

As Siwastaja mentioned, layers are usually treated as pairs, but there are always exceptions.  You may have heavy copper on one side due to high dissipation components or, depending on rise times on the board, you may want to retain a layer as a shield so that from a mid level to bottom you have:

power plane --- signal (perhaps with clock distribution) --- ground plane (also acting as shield)

With good treatment as signal matched with reference layer, design should be good on EMC (many other consideration remain, of course) but there are times when you may want to "bury" very fast signals.

Symmetry in the board stackup is also a good objective for thermal / mechanical reasons to prevent warping but any competent fab house today can work with your needs.  I've done odd layer counts in special circumstances without any problem.

[Faringdon]

Hi,
Isnt it strange that this video doesnt contain advice that  adjacent signal layers in multi-layer PCBs, should comprise traces going one way on the one layer, and traces going at 90 degrees to that, on the adjacent layer?



...after all, the cross-coupling between signal traces that are at 90 degrees to each other is much less.....and the above video often talks about the ills of cross-coupling between traces on different layers.
So why do you  think did they not mention the "90 degree thing"?

[Fronberry]

You're right that, if unavoidable, signals on directly adjacent layers should generally be routed perpendicular to each other.... but typically designers try to avoid having adjacent signal layers if at all possible.

Typically, you aim for a symmetric (with respect to the center layer) stackup that always has an adjacent GND plane for signals to capacitively couple to.  This doubles as usually being the cheapest type of stackup to manufacture.

[Faringdon]

Thanks, on crowded boards, the above video recomends  putting up with adjacent signal layers, and having gnd pours around the signals. Then using (presumably) buried vias to connect the bits of GND pour to the main gnd pour layers.......if not buried vias then there would be a lot of thru vias, which cuts up the board a lot.

The above video also says that you dont get off-board radiative problems above 300MHz, because off-board cables are usually >0.5m in length....but i see plenty of eg 20mm ribbon cables coming off boards, so i dont know why he says <300MHz for cable radiation problems?

Also, the above video says that for >4GB signals, you shoudlnt use FR4.....but then what substrate would you use?

This says use RO4003, but i cant find a comparitive chart showing dielectric consstant and cost, and signal frequency.
https://www.microwavejournal.com/blogs/1-rog-blog/post/23743-selecting-pcb-materials-for-high-speed-digital-circuits

[McBryce]

Thanks, on crowded boards, the above video recomends  putting up with adjacent signal layers, and having gnd pours around the signals. Then using (presumably) buried vias to connect the bits of GND pour to the main gnd pour layers.......if not buried vias then there would be a lot of thru vias, which cuts up the board a lot.

The above video also says that you dont get off-board radiative problems above 300MHz, because off-board cables are usually >0.5m in length....but i see plenty of eg 20mm ribbon cables coming off boards, so i dont know why he says <300MHz for cable radiation problems?

Also, the above video says that for >4GB signals, you shoudlnt use FR4.....but then what substrate would you use?

This says use RO4003, but i cant find a comparitive chart showing dielectric consstant and cost, and signal frequency.
https://www.microwavejournal.com/blogs/1-rog-blog/post/23743-selecting-pcb-materials-for-high-speed-digital-circuits

PTFE (Teflon) is usually used for high frequency PCB's.

McBryce.

[Psi]

Hi,
With a 6 layer PCB, would you agree, that generally the following regime is optimum…..

you have a top layer for components.
Then one layer for ground
One layer for power.
Then one layer for inner layer tracks  running in direction “A”.
Then one layer  for inner layer tracks running in a direction at 90 degrees to “A”.

Then a spare layer, likely the bottom layer, which you can make another ground.

I tend to make one inner layer VCC, all other layers GND fill, and then start filling them up with traces from top down.
Only starting to use the next layer down when I find adding a trace to any of the above layers is starting to make a mess.
When i'm done I look back through all layers and move any traces between layers where doing so would make things tidier.

Of course, on my last 6 layer PCB all layers were high current 3oz copper for moving around 12V 150A, but that was a special case. 

[asmi]

The thing about 6 layer board is that it's always a compromise. If you need to have 4 signal layers, than you aren't getting plane capacitance and you will have to be super-careful about changing a reference plane from ground to Vcc - and contrary to popular belief, reference plane does not have to be ground, it could be Vcc just as well as long as certain conditions are met. If you do want close parallel Vcc and gnd planes, you have to forego 4 signal layers.

If you want both - you will have to go for 8 layer PCB. These will allow you to have both, but you will pay for it in the literal sense - they cost about 30-40% more than 6 layer boards for prototypes, which can be significant if you don't plan to have a big production volume. In volume the price of PCBs is insignificant, so in that case you will probably want to choose 8 layers as to have less EMC/SI problems because your design will be more robust. That said, I have successfully implemented a number of PCBs with DDR3 and multi-GB serial links on a stackup I've mentioned above, so it can be done if you know what are you doing, and you keep in mind limitations of such approach while designing such boards.

[NorthGuy]

There are different factors, considerations, rules. Of course, everyone wants to lay out the perfect PCB where all the factors are considered, all the rules obeyed etc. But you cannot do this, not in the real world. You will have to disregard some of the factors, violate some of the rules. So, chose the factors which are important to you and design your board accordingly.

For example, if you have fast signals which require impedance matching, design accordingly - use thinner prepregs between signals and reference planes - this way you can get away with thinner traces and shorter distances between traces, or better yet sandwich the signal between reference planes. But don't do that if you don't need impedance matching - rather minimize the number of plains and spread your signal layers apart as much as you can - this way you can use more more signal layers.

Or, if you expect thermal problems, create big areas of thicker copper, use lots of vias to facilitate the spread of the heat. But don't do this if the heat is not a problem. Rather save space for signals.

If you want your traces in adjacent layers to run perpendicular to each other, but you cannot really do that for some reason, evaluate the magnitude of cross-talk and figure out if your desire for perpendicular wires is reasonable, and if it is, evaluate whether it can be solved by other means, such as putting wires further apart. Don't worry if "gurus" talk or don't talk about this. The processes on your board are governed by laws of physics, not by opinions of the experts.

[TomS_]

About Stackup I use some concepts taken from this video with Robert Feranec and Rick Hartley below but also from a document I keep since college.

Robert Feranec also has a really good video series analysing an 8 layer server motherboard.

There are a lot of good hints and tips in there.

I rewatch it every so often, and although I don't design high speed boards, there is still so much to learn in general about how to treat signals well, and mind blowing facts about what it does take to design high speed boards.

Highly recommended.