Hobby IC fab (Not Home Fab)

[yanir]

Hi, I'm curios about the cost of IC fabrication. I've seen that there are some people here in that industry.
I'm sure there are many factors that go into the cost of production, so if I had the simplest digital design is it possible for a hobbyist to play in this world? How much would it cost? What minimums would I need to produce?

[free_electron]

eh .. not feasible ...
FPGA's are the closest you are going to get to 'rolling your own chip'.

unless you can piggyback on a multiproject wafer such as a Mosis project ... not do-able...
The maskset alone will kill you... typical masksets for current technlogy run 1.2 to 1.5 milion dollars ...
And that just gets you the 'mask'.. you haven't even launched a single wafer yet ...

Even if you would go with an old technology ( provided you can find a fab that can still run those ) and you restrict yourself to 1 metal layer , 1 polylager and a couple of implants... you are looking at 6 to 7 masks ... about 250K$ should get you there...

There is one option though : if your design is pure digital you can go with a sea-of-gates provider. Actel , AMIs and some others still do this. these are 'half-baked' wafers. only the top metallisation is missing. so think of it as a box of lego's. there are all sorts of gates and flipflops. you design using their library, create the wiring and they create 2 metal masks. so with 70k$ you are there ...
now you are faced with another problem : 1 wafer holds , dpeending on wafer and die size, hundreds to tousands of these chips... and they do not launch 1 wafer. the batch is 50 wafer at a run ... so you end up with a pile of devices. you just forked over 70 in mask costs + the device cost + engineering cost and you sit on a pile of untested parts ...

not an easy endeavour ....

[yanir]

not an easy endeavour ....

Doesn't sound easy at all. Part of the attraction  . But I might have to wait on it. I did find mosis's site. Is that an option? How does that work?

[yanir]

follow up question...

. you just forked over 70 in mask costs + the device cost + engineering cost and you sit on a pile of untested parts ...

not an easy endeavour ....

How do IC startups test designs? At these costs failure isn't an option.

[free_electron]

they  uses a shared-wafer foundry like a mosis project http://www.mosis.com/


but the costs are still several hundred K $ to run a single batch. silicon startups are well-funded ... and they get really good simultaion libraries and really good simulators tied to the target technology. ( we're not talking lt-spice here but tools like Eldo ... yearly licence of that alone is a couple of 100k$ )

your best option as startup is to use the Tanner tools www.tannereda.com and get from Mosis the scalable design library .
Anything else requires signing of NDA's with the Fab's... not something that is easy .... and the devlibs are going to be for Cadence or Mentor toolchains which cost both arms , both legs and your 2 firstborn children. ....

[olsenn]

I would sell my right nut for a second left nut

[Mechatrommer]

and the devlibs are going to be for Cadence or Mentor toolchains which cost both arms , both legs and your 2 firstborn children

humans are easier and cheaper to fabricate these days.

[EEVblog]

but the costs are still several hundred K $ to run a single batch. silicon startups are well-funded ... and they get really good simultaion libraries and really good simulators tied to the target technology. ( we're not talking lt-spice here but tools like Eldo ... yearly licence of that alone is a couple of 100k$ )

We talk a bit about this with the CTO from the startup Energy Micro on next weeks AmpHour.

Dave.

[jmelson]

not an easy endeavour ....

Doesn't sound easy at all. Part of the attraction  . But I might have to wait on it. I did find mosis's site. Is that an option? How does that work?

MOSIS combines designs from dozens of groups onto one reticle (about 25 x 35 mm).  This reticle is then step and repeated across the wafer, making maybe 50 copies of the reticle.  Depending on number of subscribers for a particular run, you may get some modest number of instances on the reticle.  So, you can end up with several hundred of YOUR design made per wafer.  (And, they always run a few wafers just to prevent one oops from ruining all of that run.)  You pay a fee based on area and number of chips ordered.  Minimum order is one "lot", typically 40 ICs at MOSIS, and in some processes that will run something like $7000, unpackaged.
Our chips are always bigger than the minimum, so they typically run $18000 to $25000 for the first batch of 40.  Additional batches are something  like $3000 per additional 40 parts.

One other thing, you need to use QUITE expensive design software to generate the design files and do simulations.  The commercial versions of this software run something like $250,000 per seat, with a yearly license to keep it working.  We use a university license version, but that restricts the chips to NON-COMMERCIAL use.
There are some open-source design software, but I have no idea if any of those are compatible with MOSIS or the foundry's design kits.

Purely digital circuits can be synthesized without "getting your hands dirty", but analog is done by carving each transistor by length and width, and massive amounts of simulation.

Jon