I have some 0.5mm pitch parts on a board - a QFN and an FFC connector - and I'm concerned that my paste stencil apertures for the pads on these parts are too small. I hate dealing with these fine-pitch parts as I've always had problems in the past. I want to put some effort into making sure I've
really got things right this time.
I've been reading IPC-7525A, where it talks about the ideal aspect ratio and area ratio for stencil apertures; the reason being, as I understand it, so that paste easily separates from the stencil and stays on the board. Aspect ratio being the ratio of aperture width to stencil thickness, and area ratio being the ratio of aperture opening to aperture wall area (i.e. the vertical sides of the aperture). As a general guideline, the aspect ratio they give is >= 1.5, and area ratio >= 0.66.
The pads on the QFN are 0.85x0.26mm, and the FFC are 1.2x0.3mm. With my default paste shrink of 0.05mm, that gives apertures of 0.75x0.16 and 1.1x0.2. The ratios for those are 1.07/0.44 and 1.33/0.56, which falls short of the recommended values.
If I go ahead and use these aperture sizes, am I going to definitely have problems with paste application?
In order to meet the guideline figures, I would need to reduce my paste shrink on the QFN to zero (i.e. so aperture same size as pads) and 0.03mm for the FFC. The former worries me as it seems like too much paste for such a tiny pad.
I don't want to then have bridging problems because of too much paste!
In the IPC-7525A document they also have charts of acceptable area ratio for varying stencil thickness. I plan to have my stencils made at JLCPCB, and their default stencil thickness is 0.15mm (approx. 6 mil).
My revised aperture size puts them both just about on the middle red line for "Electroformed or Laser" stencils. I presume the different stencil fabrication techniques correspond to varying levels of roughness of finish of aperture, which is the only thing I can think of that would affect paste release. I believe JLCPCB stencils are laser cut, so that chart data should correspond, right? JLCPCB also recommended a different, optional, polishing process ("Etching Polishing") for component pitches of 0.5mm or less. They explain it as having a de-burring effect. So, if I order my stencil with that option, it should definitely put me well within the red line on the graph?