EEVblog Electronics Community Forum
Electronics => Manufacturing & Assembly => Topic started by: Wilson__ on September 30, 2024, 03:58:50 am
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Do you use teardrop in PCB layout? If so:
Where you use it, PTH pads, Vias, (may be not) SMD pads, Track to track?
Do you use it only on default 0.2mm signal track width (and not on wider power tracks)?
Many thanks
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I use it on production designs, on request.
Altium's automatic generation seems good enough, and I haven't heard any push-back from it. Mind, production may optimize the design further after I'm done with it.
It's not very meaningful for proto designs, if that's what you're doing. It's a production yield optimization -- or, if your footprints (mostly thru pad annular rings) are so insufficient that proto yield even is poor, you should probably address that first(!).
Tim
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I use it on production designs, on request.
Altium's automatic generation seems good enough, and I haven't heard any push-back from it. Mind, production may optimize the design further after I'm done with it.
It's not very meaningful for proto designs, if that's what you're doing. It's a production yield optimization -- or, if your footprints (mostly thru pad annular rings) are so insufficient that proto yield even is poor, you should probably address that first(!).
Tim
Apparently, pcb factories are quite good since usb-c and 0.5mm IC are widely used nowadays.
KiCad defaults to no teardrop for 0.2mm track width. May be suggesting no teardrop???
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I tried the teardrops feature in KiCad for the first time the other day. I did it for no reason other than just curiosity.
The attached screenshot shows the KiCad config I used for the through-hole pads for a typical 0.1" pitch pin header; you can see the result in the photo (JLC PCB).
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I do, even in prototypes if I can.
It makes the junction between tracks and vias more reliable, especially when you start soldering on it.
On prototypes often you have to solder/desolder stuff many times, and a tiny track can easily break, with a teardrop it became more robust.
The only downside, when I used it on altium, is that you have to remember to regenerate them every time you do some change on the PCB. Otherwise you can end with random poligons here and there.
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I build PCBs from multiple designers/clients in a wide range on industries including automotive and instrumentation. I honestly couldn't recall seeing a tendency to use teardrop by any of them, certainly nothing as extreme as the example shown by @shabaz. Theory aside I don't think its ever shown up as a statistically relevant point of failure, shorts or other process failures are far more common.
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Don't use teardrop, and don't see the need to.
There are situations where a SMD part or connector ended up not having enough strength and delaminates. But you can fix that at an individual component level and tweak the footprint. Or get glue to be applied. I would not do it at an entire board level, too much hassle.
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Just remembered I used that teardrops feature on a second board too.. they were ordered around the same time.
In KiCad 8.0 it's a config setting at the pad level, either in a component, or in the PCB editor.
It for sure is a bit of a novelty in my case.
Maybe handy for the "vintage" look that old single-sided PCBs with no through-hole-plating used to have. Or maybe on a proto board where a user may very frequently unsolder and re-solder perhaps, although as @thm_w mentions, that's resolvable in a normal footprint anyway.
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Teardrops are pretty much necessary to acheive good yield if you have minimum size annular ring and require IPC Class 3 for the boards. For lower class boards it may not be necessary, but preferable as it reduces risk of a weak connection between trace and via.
The purpose of the teardrop is to avoid that the track is cut when drilling vias. For tracks and SMD pads, the value is limited but I usually apply them to reinforce connections between narrow tracks and large pads, which is a risky point for cracking of traces due to thermal cycling/fatigue. Relevant for high-rel things, in most cases irrelevant...
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Not really. The only one who really knows if teardrops are useful is the fabricator of the PCB. And they will usually add them on their own, if necessary. The only exception where I maybe add teardrops myself might be flex-boards. But that depends on the application.
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I use it on PCBs if they have any traces under 6mil. And if I use it then I use it on everything.
I don't recall the exact settings, whatever the Altium default is
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I have seen evaluation kits for MPS power product use teardrop when using terminal connections for power, et. al.
https://www.monolithicpower.com/en/evq4326-r-00a.html (https://www.monolithicpower.com/en/evq4326-r-00a.html)
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I use a basic setup in KiCad, and whatever it generates automatically. I also use rounded pads. This doesn't matter much for the boards, but it does matter if you get a stencil, where sharp corners and anything remotely pointy is a detriment.
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I have seen evaluation kits for MPS power product use teardrop when using terminal connections for power, et. al.
https://www.monolithicpower.com/en/evq4326-r-00a.html (https://www.monolithicpower.com/en/evq4326-r-00a.html)
Don't always trust eval boards to be good layouts, most are, but some are just done by interns.
I don't see much value in the teardrops they use, normally I would use a plane if its high current trace instead.
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I do use them on via's to prevent break-out when they drill. On IPC Class 3 boards this leads to higher yields.
On flex board you should use them on both via's as well as on pad's
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Olimex makes a bunch of Linux SBC's based on allwinner chips, and they also open sourced the complete KiCad project for their boards. The boards were designed before KiCad had full support for teardrops, and therefore they used short thick track stubs for the I/O connector.
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I use them on through hole connectors - anything that's subject to mechanical stress and a risk of cracking where that stress might be concentrated.