General PCB Manufacturing Pros and Cons

[asmi]

OSHPark is by far the best for small boards in small quantities.  Quality is excellent. They have reasonable stackup for 4-layer boards and ENIG. And their tolerances are good for 0.8mm BGA (5 mil trace and 8 mil drill). I've just made PIC32MZ DA test board and it turned out great. I paid only $40 with free shipping! They don't have 6-layer though, and everything which is bigger getting pricey.

Are you sure about that? Their website says 5/5 traces with 10 mil drills and 4 mil annual ring - you can't breakout 0.8 mm BGAs with that process: 32 (=0.8 mm) - (10+4*2)= 14 mils between vias, which is 1 mil short (in reality a bit more, because I rounded 1 mil down to 0.125 mm, while it actually is 0.127 mm) of 15 mils (5 mil track + 2*5 mils spacing) needed to route a track between vias. Unless breaking out just outer 3 rows is good enough for you.

[NorthGuy]

Are you sure about that? Their website says 5/5 traces with 10 mil drills and 4 mil annual ring - you can't breakout 0.8 mm BGAs with that process: 32 (=0.8 mm) - (10+4*2)= 14 mils between vias, which is 1 mil short (in reality a bit more, because I rounded 1 mil down to 0.125 mm, while it actually is 0.127 mm) of 15 mils (5 mil track + 2*5 mils spacing) needed to route a track between vias. Unless breaking out just outer 3 rows is good enough for you.

I broke out every pin. You're right they have 10 mil drills, but annular rings are 4 mil, so it boils down to the same size of via pads - 18 mil. I cheated and made them 17 mil, and it worked just fine. Of course, it is impossible to see because it is on the inner layers, but here's how it looks from the top. You can still see some 17 mil vias with holes although even these are under the solder mask.

[asmi]

I broke out every pin. You're right they have 10 mil drills, but annular rings are 4 mil, so it boils down to the same size of via pads - 18 mil. I cheated and made them 17 mil, and it worked just fine. Of course, it is impossible to see because it is on the inner layers, but here's how it looks from the top. You can still see some 17 mil vias with holes although even these are under the solder mask.

Here we go. That's what I suspected. Still it's not a viable option for me as my board are usually rather large (FPGAs need several power rails and it's not a good idea to have them off-board because that degrades converters' transient response), so it still is cheaper to order them at the likes of PCBWay (and I need a stencil as well). I did cheat in my Artix-7 board as well and made annual ring of only 0.125 mm instead of 0.15 mm as they require, but boards came out OK (at least ones I've checked).
And for DDR3 memory I will need 6 layers by the looks of it - at least so far I was unable to successfully route it on 4 layers.

[NorthGuy]

I did cheat in my Artix-7 board as well and made annual ring of only 0.125 mm instead of 0.15 mm as they require, but boards came out OK (at least ones I've checked).

This is actually 2 mil you have cheated. I only cheated 1 mil

And for DDR3 memory I will need 6 layers by the looks of it - at least so far I was unable to successfully route it on 4 layers.

Micron has a technical note: "TN-41-08: Design Guide for Two DDR3-1066 UDIMM Systems"

It is about DIMMs (and 2 of them), so probably not exactly what you're doing, but they suggest 4-layer board, they discuss routing, impedance etc. May be of interest to you.

I had an idea of 256-pin Artix-7 with SO-DIMM. I wanted to place Artix-7 on one side and SO-DIMM on the other side. Half of the DQ lines from the same group would go on the top layer (where FPGA is) then they would have vias next to the far end of the SO-DIMM socket. The other half would go straight to the bottom from the dogbone, then would travel the bottom layer and would connect to the near side of the SO-DIMM connector. This way it is easier to match lengths and it is only one via for each line.

I started this it, and I even routed three groups, but then I abandoned this idea and decided that I would better go with 484-pin Artix-7 and 6-layer board. I would even go with 676-pin model, but they're expensive and have horrible pinouts.

What was the problem with your routing?

[mrpackethead]

Im doing a BGA design right now ( 4 layer, 389 pin )..  .8mm pitch.  Forutnatly the designers of the chip have done a good job of laying it out..  I've gone for via in pad,  it will be .2mm vias.. This lets me use 0402 caps for decoupling rather than 0201, which pushes my assembly process just a bit too far.

[asmi]

This is actually 2 mil you have cheated. I only cheated 1 mil

But to be absolutely honest I've done this before multiple times with both PCBWay and allpcb, and in all cases boards came out good, and they never said anything about it. So I was relatively certain of favorable outcome. I just thought that I'm the only one who plays chicken with PCB houses

Micron has a technical note: "TN-41-08: Design Guide for Two DDR3-1066 UDIMM Systems"

It is about DIMMs (and 2 of them), so probably not exactly what you're doing, but they suggest 4-layer board, they discuss routing, impedance etc. May be of interest to you.

Thanks.

I had an idea of 256-pin Artix-7 with SO-DIMM. I wanted to place Artix-7 on one side and SO-DIMM on the other side. Half of the DQ lines from the same group would go on the top layer (where FPGA is) then they would have vias next to the far end of the SO-DIMM socket. The other half would go straight to the bottom from the dogbone, then would travel the bottom layer and would connect to the near side of the SO-DIMM connector. This way it is easier to match lengths and it is only one via for each line.

That won't work, because DDR3 controller requires all pins to be in the same IO column. And you'd better not use right column (IO banks 14 and 15) because they contain configuration pins which are required to be on certain voltage domain during bootup stage (like QSPI flash pins for example that can only be 1.8 or 3.3 V depending on what IC do you use). So while it's theoretically possible though the use of voltage translators, MIG datasheet and wizard strongly advise against it.
But because left column has one of two IO banks only partially bonded out (specifically only one DQ group of the bank 34 is fully bonded out, and other one partially), you can only use a single x8 DDR3 chip with that package as MIG wizard doesn't allow to pick anything from bank 34. So unless I'm missing something (or will be willing to play games with voltage translation), you can't have anything other than x8 chip with that package.

I started this it, and I even routed three groups, but then I abandoned this idea and decided that I would better go with 484-pin Artix-7 and 6-layer board. I would even go with 676-pin model, but they're expensive and have horrible pinouts.

I'm thinking about making a devboard out of 484 package on a 6-layer using 0.1/0.1/0.2 mm process as this will allow me to fit two traces between vias, which in turn should allow to fully route out all pins on the package without major hassle. The reason is I want to make a Gameboy-kind of device and FPGA will need to drive LCD via 24-bit parallel port (+ pins for the touchscreen), and that is in addition to the memory (which by itself will consume two IO banks because of IO voltage requirement), and since two banks will be involved, I might as well go all the way and route 4 byte groups for 32bit-wide bus - this will allow me to practice fly-by routing for address/control lines too

What was the problem with your routing?

A couple of issues - one was that I couldn't come up with the way to route out all lines of ADDR/CTRL group on a single layer while maintaining length matching. Another one was that traces took all the space on the bottom layer, so I had no space to put decoupling caps for that bank, and from what I understand that is a big no-no especially when you have so many fast switching pins in the bank.
Placing ADDR/CTRL bus traces on different routing layers would not work because of the stackup I've chosen (signal-power-signal-ground, which is, while not optimal, gave me more routing space in the critical breakout region as decoupling caps did not interfere with signal traces). The problem here is that propagation delay for inner and outer layers is different because of different effective dielectric constant of the air vs prepreg.
The bottom line is I wasn't able to route it while complying with all DDR3 memory interface requirements and recommendations, and while it might just work, spending $200 or boards + ~$100 on components to find out seemed like not the best idea.
With that said, I found that AM3354 SoC from TI in "Via Channel" package was specifically designed to be routed out on 4 layer boards, and it has DDR3 interface among others, and this sounds very convincing for me to just take the risk and give it a try. So I might as well do just that - but a little later, as my purchase of Orcad PCB Editor Pro will wipe out all my hobby money for the next several months, and by spending more I run the risk of being kicked away from home by my wife But at least with that CAD package I can actually run IBIS simulations and be reasonably sure it will work if the sim will say so. So stay tuned!

[NorthGuy]

That won't work, because DDR3 controller requires all pins to be in the same IO column. And you'd better not use right column (IO banks 14 and 15) because they contain configuration pins which are required to be on certain voltage domain during bootup stage (like QSPI flash pins for example that can only be 1.8 or 3.3 V depending on what IC do you use).

I was going to run all banks at 1.5V. According to my reading of the config docs this should be Ok. Then I would use level shifters for the flash, PIC, and SPD. I also wanted to add Ethernet PHY running at 1.5V. SO-DIMM would require 8 byte groups, so I would completely use banks 14, 15, and 35, with bank 34 left for test pins. This was meant to be a test board.

I was going to go by Micron recommendations (signal-power-ground-signal). This would give me two signal layers with the same impedance characteristics. The capacitors are certainly very important at this speed, but I was going to insert them inter-layer outside of FPGA - not much choice here. Xilinx says within an inch of FPGA, so it might have worked Ok. You may try that too. And if you go (signal-power-ground-signal) you can split the control lines between layers. Also Address/Control lines are less important than DQ/DSQ, so you can give them more slack.

Now I think of the 484-layout. They have banks 14,15 and 16 together which I want to run on 1.5V and connect all the stuff to them. Then I can test the core and once this is done, I can grow useful board from the other side - banks 34, and 35 (and 13 if I get a bigger chip). I'll go with (slow signal-power-signal-power-signal-ground) layers. This also will give me two signal layers with the same impedance characteristics, and since they're striplines, I will be able to get away with much more narrow traces. So, I think SO-DIMM is well within the reach.

I already have a component box with enough stuff to build 5-6 revisions. I don't have much time to design the board though

[asmi]

I was going to run all banks at 1.5V. According to my reading of the config docs this should be Ok. Then I would use level shifters for the flash, PIC, and SPD. I also wanted to add Ethernet PHY running at 1.5V. SO-DIMM would require 8 byte groups, so I would completely use banks 14, 15, and 35, with bank 34 left for test pins. This was meant to be a test board.

Now I'm looking at schematic of my board, and I noticed that I don't use any of bank 15 pins for config (because I use QSPI flash), as for bank 14 the only "special" pin (aside from QSPI ones obviously) is PUDC, which controls whether IO pins' pullups are going to be on or off during configuration. I also have main clock input here, but this is irrelevant as it can be pretty much any MRCC pin. So what you're saying might actually work. Gotta verify this in Vivado though as I've already made enough stupid mistakes by choosing wrong pin for the clock on the first spin of the board Actually that first spin was such huge disaster as I couldn't believe just how many mistakes I've made (and still do - even in rev 2 I use SRCC pin for clock instead of MRCC ) I guess I was too scared by MIG's warnings
BTW - what would you need PIC for? Microblaze seems plenty powerful, and you can stuff several of them inside FPGA if one is not enough (and you've got some LUTs/FFs to spare).

I was going to go by Micron recommendations (signal-power-ground-signal). This would give me two signal layers with the same impedance characteristics. The capacitors are certainly very important at this speed, but I was going to insert them inter-layer outside of FPGA - not much choice here. Xilinx says within an inch of FPGA, so it might have worked Ok. You may try that too. And if you go (signal-power-ground-signal) you can split the control lines between layers. Also Address/Control lines are less important than DQ/DSQ, so you can give them more slack.

Or you can expose power/gnd vias on the bottom of the board under the BGA and manually solder these caps (BGA pitch is 1.0 mm and so is the size of 0402). The reflow will likely fail in this case as solder will be wicked into vias, but manual soldering should do as a sort of poor-man via-in-a-pad. Hmm, interesting

Now I think of the 484-layout. They have banks 14,15 and 16 together which I want to run on 1.5V and connect all the stuff to them. Then I can test the core and once this is done, I can grow useful board from the other side - banks 34, and 35 (and 13 if I get a bigger chip). I'll go with (slow signal-power-signal-power-signal-ground) layers. This also will give me two signal layers with the same impedance characteristics, and since they're striplines, I will be able to get away with much more narrow traces. So, I think SO-DIMM is well within the reach.

BTW as example - here are PCBWay's standard stackups for 6-layer boards (core thickness shown there includes copper layers on both sides of it, so you gotta sub 0.07 mm to get dielectric thickness, 7628 is 0.185 mm, 2116 is 0.105):

1.6 mm version kinda sucks for high-speed design, but 1.2 mm seems alright (low-speed/gnd/hi-speed/hi-speed/power/low-speed) - Orcad calculated 0.1897 mm trace for 50 Ohm single-ended impedance, and 0.1512 mm tracks with 0.3 mm separation for 100 Ohm differential impedance (for edge-coupled traces,). Not too bad at all I would say. The only real concern is that thin prepreg between hi-speed layers - will have to make sure that crosstalk is in check.

I already have a component box with enough stuff to build 5-6 revisions. I don't have much time to design the board though

I stopped buying components "just in case" some time ago as I already have two boxes of parts which I can't remember what did I buy them for So now aside from passives and things like chip LEDs, I tend to buy parts when I actually need them. With Digikey/Mouser's next business day delivery it's not too bad.

[NorthGuy]

BTW - what would you need PIC for?

Lots of different small tasks - power sequencing, reset, communications with PC (perhaps SPD too), storing some settings etc.

Or you can expose power/gnd vias on the bottom of the board under the BGA and manually solder these caps (BGA pitch is 1.0 mm and so is the size of 0402). The reflow will likely fail in this case as solder will be wicked into vias, but manual soldering should do as a sort of poor-man via-in-a-pad. Hmm, interesting

I am not that good at soldering. I'd better put the caps on top and reflow everything. Unless absolutely necessary.

BTW as example - here are PCBWay's standard stackups for 6-layer boards (core thickness shown there includes copper layers on both sides of it, so you gotta sub 0.07 mm to get dielectric thickness, 7628 is 0.185 mm, 2116 is 0.105):

Thanks. This is a good stackup. I like 1.6mm better because it's uniform. In the quotation form, they offer custom stackup and it is just $20 extra or so. Don't know if that's true,

1.6 mm version kinda sucks for high-speed design, but 1.2 mm seems alright (low-speed/gnd/hi-speed/hi-speed/power/low-speed) - Orcad calculated 0.1897 mm trace for 50 Ohm single-ended impedance.

Strange. The online calculator for striplines ( http://www.mantaro.com/resources/impedance-calculator.htm )  shows smaller values. For 50 Ohm, it calculates 8 mil for the 1.6mm board. For the 1.2mm stackup, it calculates 7 mil if the signal layer sits against the outer pre-preg and 4 mil if the signal layer sits against the central (thinner) pre-preg.

I tend to buy parts when I actually need them. With Digikey/Mouser's next business day delivery it's not too bad.

Sometimes, you design and print a board and then you see that the part which you used is no longer in stock. I came across such situation few times. Now I order all the parts before I print boards.

[asmi]

Lots of different small tasks - power sequencing, reset, communications with PC (perhaps SPD too), storing some settings etc.

I see. I use TPS65400 to power the FPGA, it's got built-in support for sequencing (even though it's not that important with 7 series FPGAs).

I am not that good at soldering. I'd better put the caps on top and reflow everything. Unless absolutely necessary.

I usually reflow both sides as well. But in that case I'd have to use via as a pad, and reflow would likely fail in this situation.

Thanks. This is a good stackup. I like 1.6mm better because it's uniform. In the quotation form, they offer custom stackup and it is just $20 extra or so. Don't know if that's true,

I don't know either. Their calculator is kinda wonky.

Strange. The online calculator for striplines ( http://www.mantaro.com/resources/impedance-calculator.htm )  shows smaller values. For 50 Ohm, it calculates 8 mil for the 1.6mm board. For the 1.2mm stackup, it calculates 7 mil if the signal layer sits against the outer pre-preg and 4 mil if the signal layer sits against the central (thinner) pre-preg.

This is what I've got (numbers are slightly different since last time I forgot to set a proper dielectric constant - 4.29 as per PCBWay's support)

Sometimes, you design and print a board and then you see that the part which you used is no longer in stock. I came across such situation few times. Now I order all the parts before I print boards.

I try using only parts that are in stock in multiple sources. But whenever I do order parts, I usually order in quantity of 10 as usually that's where next price tier is so I will have some surplus in case I mess up assembly (unless they are super expensive parts like FPGAs - these things I usually buy however many I need + 1 just in case). For passives I usually "pad" my orders to get free shipping with full reels of 0402 components as they are very cheap anyway, and I slowly build up an inventory of them.

[Cerebus]

I don't want to be a killjoy, but you're kind of hijacking the thread guys. (I know, pot calling kettle black; I've been rather guilty of this myself.)

[NorthGuy]

I don't want to be a killjoy, but you're kind of hijacking the thread guys. (I know, pot calling kettle black; I've been rather guilty of this myself.)

Guilty

[Corporate666]

Price is NO indicator.. The cheaper fab might actually be better.   The only way you can find out is to try them out...     And its the 'total' quality that you've got to take into account. thats ontime delviery, easy to use.. If i have to spend hours sorting out drama because its too hard,  then it coudl be free, but it woudl still be expensive if that makes sense.      I've found that for all my 'basic' PCBs ( thats stuff that is 4 layer, .15/.15 and .3mm min vias ) that AllPCB have done a really good job.   Mostly on time, they ahve owned their mistakes and they are easy to communicate. It took a bit of time to work otu what they were about though, and all their changes dont' make it easy.

Oh, I absolutely agree.  My point was that if a PCB fab is more expensive because they are spending more man-hours making the boards to a high standard, or because they have better equipment or tighter tolerances causing more scrap, then to many customers, that is a selling point and they will gladly pay more. 

Being more expensive is fine, provided I am getting something more for my money.  I dislike when a company is more expensive but tries to hide it (like by having add-on fees that aren't shown when you're browsing the site and price-checking). 

I posted an experience with PCBWin and I was exceptionally happy with them.  I ordered 1000pcs of a small board.  They were a bit more expensive, but not by much... and those 1000 PCB's represent $50,000 worth of revenue to my company, so I couldn't care in the slightest if the PCB order was $220 vs $190 somewhere else.  Having the boards done right with good communication and options I can choose from (as posted above) is worth that $30 and more.  Shipping out even 2 or 3 bad PCB's or having to rework PCB's that are shoddy from the get-go will eat up 100 times the cost savings on the initial order.

[mrpackethead]

I posted an experience with PCBWin and I was exceptionally happy with them.  I ordered 1000pcs of a small board.  They were a bit more expensive, but not by much... and those 1000 PCB's represent $50,000 worth of revenue to my company, so I couldn't care in the slightest if the PCB order was $220 vs $190 somewhere else.  Having the boards done right with good communication and options I can choose from (as posted above) is worth that $30 and more.  Shipping out even 2 or 3 bad PCB's or having to rework PCB's that are shoddy from the get-go will eat up 100 times the cost savings on the initial order.

But it seems that just because you pay $30, $80 or -$20 in comparison to another board house it is no indicator of the quality.   Its a bizzare and strange market.