Silkscreen clean up from itead/seeed/etc?

[mrflibble]

Does itead or seed or <fill in> clean up the silkscreen? By which I mean, if the silkscreen covers exposed solderpads, do they remove this silkscreen or not? Never? Sometimes when they feel like it?

I also read the following on this here page with itead quirks.

"Don't assume they [itead] will perform Silkscreen Clean-up for you, because you may end up with silkscreen covering your exposed copper if you do. Specifically lines seem to be cleaned up ok, but text seems to be left alone, so you can get results such as this ..."

This has sort of been my working assumption. Text will not get cleaned up, lines will (at least I hope so XD). The reason is that quite a few of the components I used had silkscreen (lines) over the pads. Cleaning up all the lib parts at this point simply was not a viable option since that would take far too much time.

Another option that I can think of is to do some clever operations on the gerbers, but at this point in time it was safer for me to hope itead cleans up silkscreen lines. Probably safer than messing with the gerbers myself and then stuffing it up.

Anyways, I was wondering what your experiences are with itead silkscreen cleanup in particular, and seeed/The Rest [tm] in general.

[Smokey]

I've only used Iteed.  If they do look at the layers, then they don't put much effort into it.  I've had them put silk right on pads when I forgot to clean it up first.  It's my own fault after all

The worse problem is silk alignment, which they are pretty terrible at.  Make sure you don't put silk too close to pads and expect them to be dead nuts on.  Watch the line width of silk screen too.  If it's too small it just comes out as a bunch of dots.

All that said I don't plan on switching any time soon since they are so cheap.  It's not like I'm doing super complicated or production level boards with them though.

[mrflibble]

Thanks! That's good to know. Not what I hoped to hear, but can't have it all. In that case I can probably count on having silkscreen on several pads. Oh well, if so that was a calculated risk. I really wasn't going to put hours of extra effort into cleaning all that up. This was a prototype board, so if I have to scratch away some silk so be it.

The question was more for future reference ... So for the next board I'll have to have a good method to clean up the gerbers.

Is there some handy gerber tool with which I can do that? Essentially it would be something like:
- copy solder into tmp layer
- expand tmp layer by some margin (say 10 mil)
- mask off silk with tmp layer

Preferably under linux, but I'm not too picky about that.

[daveatol]

That seems like quite poor form if they are printing the silk overlay over the pads. I've used Seeed (and other online providers - not Itead however), and I've never had the overlay printed on the pads

[c4757p]

I don't think it's poor form, but then, I'm not too experienced with PCB manufacturers. Seems to me that proper form would be to do precisely what you tell them to do - if your Gerbers have silkscreen over exposed copper, then so will your PCB. Don't most packages have an option to clear silkscreen from the pads when generating the Gerbers, anyway?

[mrflibble]

Now that you mention it, you're right. I'd rather have they just manufacture it exactly as specified. Or if not that, send an email for clarification. And since I do not expect the latter at this price point, best if they just produce it as is.

As for cleaning up the gerbers ... I used Altium, and couldn't find any such option in the jobfile description for gerber output. But it's entire possible that I'm blind and missed the magic button.

[daedalus]

MrFlibble, if you use Altium you shouldn't be able to pass a DRC if you have silk over pads, and the appropriate clearance rule set. AFAIK there isn't a tool to automatically clear such errors, but their locations will be indicated when you run the DRC.

[mrflibble]

Well, there is if you purposefully disable precisely these silk clearance rules. Not because because I think that this is the best way to go. But simply because the amount of effort I would have to put into fixing all the silk clearance violations would be prohibitive. Most were related to silk over silk. What's that? silk screen line X over silk screen line Y? Oh noooez! *ignore* And then there were some that were lines over pads. Those were the ones that I would like to have fixed, but they were in already existing library parts that I didn't really want to have to fix.

Bummer that there's no tool in altium to fix that. Any external gerber tools? Operation wise it's not super complex, it's just that I am still finding my way around the tools.

[Smokey]

Fixing something like clearance issues of any kind after you have already generated the gerbers sounds like a really bad idea to me.  If you ever had to do another revision and regenerate the gerbers, you would have to post process them by hand all over again.  You should be able to set up DRC rules exactly how you want them.  Silk-Silk, Silk-Pad, Silk-whatever.  I can't believe you have so many components on the board, let alone ones with silk clearance violations, that it would actually take much time to fix after the DRC shows you exactly where they are.  Besides as you are laying out the board you HAVE to touch every component at some point when you are routing it.  Some might slip though when you reroute stuff, but it shouldn't be that many.
 
Some of the big board houses in the states will clean up silk on pads for you.  They run their own DRC on your boards after they get them to make sure they meet whatever process spec they are running.  I've never had advanced circuits put silk on a pad and we use them for quick turn prototype stuff all the time (and ya, I have been known to accidentally leave silk on pads in RevA gerbers).  Another thing they will usually do is if you specify the mask swell too small, they will bump it up to the minimum they can do.  We usually do the standard spec deals with AS so things like that aren't options.  I'm not sure what they would do with swell on a custom spec job.  Advanced Circuits makes some good boards.

[HackedFridgeMagnet]

Kicad has a plot option,
'Subtract solder mask from silkscreen'. Aint that neat.

I can't believe Altium wouldn't have similar.

[mrflibble]

Fixing something like clearance issues of any kind after you have already generated the gerbers sounds like a really bad idea to me.  If you ever had to do another revision and regenerate the gerbers, you would have to post process them by hand all over again.

BY HAND?!? @_@ Have you gone clinically insane good sir? I am far far too lazy to do anything as silly as that. It is either scripted or bust! Put another way, I refuse having to do something as tedious as that. Either a systematic solution or screw it. Because as you say, should I regenerate gerbers, then the cleanup has to be done again. If the cleanup can be done automatically ... fine. By hand ... no way.

You should be able to set up DRC rules exactly how you want them.  Silk-Silk, Silk-Pad, Silk-whatever.  I can't believe you have so many components on the board, let alone ones with silk clearance violations, that it would actually take much time to fix after the DRC shows you exactly where they are.  Besides as you are laying out the board you HAVE to touch every component at some point when you are routing it.  Some might slip though when you reroute stuff, but it shouldn't be that many.

The silk related DRC rules are fine. To wit, the rule entry is fine. And I disabled said rule entry because of see previous.

As for component count, I don't have super duper many components on the board. Maybe I am just using the wrong library components. Anyways, the components I had to make my own lib entries for are fine (of course ). But some of the ones from other libs had said silk screen issues. And no I am not going to fix other people's libraries because of silly stuff like this. I'd rather look for better cleaner libs that don't require a cleanup. After all, the point of using already existing libs is less work, not more work.

Anyways, graphically speaking the operation of removing silk from solder is pretty trivial. It's just that I am still finding my way around the altium + gerber related tools. If gerbers were bitmaps I'd whip up a script in under 1 hour. So I am still secretly hoping that the option is lurking out there somewhere, and that I am just totally blind. 

[daedalus]

if you are getting silk-on-pad drc violations from the bundled component footprints, then you have the minimum clearance set too high! the default settings altium comes with will cause this to happen, just reduce the clearance until the only errors you see are actual silk over pad issues in your design.

EDIT: i use silk over component pad clearance of 0.15mm and silk-silk of 0.1mm, which seems ok with all the library parts i use

[mrflibble]

if you are getting silk-on-pad drc violations from the bundled component footprints, then you have the minimum clearance set too high! the default settings altium comes with will cause this to happen, just reduce the clearance until the only errors you see are actual silk over pad issues in your design.

You're right, I was using default clearance. For the next PCB I adjusted the silk related clearances to 0.1 mm, and that looks a bit better.

Incidentally, the PCBs with all the silk violations arrived today. And they all look to have turned out fine. Even for the bits that were actual violations, like silk of a large radial cap that went over wide tracks where I opened up the soldermask. But no issues whatsoever. The silk just stops short of the solder as you'd expect, and no negative effects on the tracks that I can detect with the naked eye.