JLC PCB stackup layer spacing

[radar_macgyver]

JLC PCB has an FAQ entry about stackups with pictures indicating a 0.18 mm prepreg between top and inner1 (for a 4-layer).

However, they also have .stackup files suitable for Altium that, for 4-layer boards, show two different stackups. The same two stackups are shown here. Here, depending on the fiberglass weave, one gets either 0.1 mm or 0.2 mm between outer and inner layers.

I took some measurements from Dave's section of the board (loaded the image into an editor, counted pixels between layers and scaled by the 1.6mm board thickness); it seems to show something more like 0.22mm. Given the image resolution, the error is ~0.05mm assuming no parallax.




Does anyone know which one is actually used for 4-layer prototypes? I'm hoping to make a microstrip or CPW to route some traces at ~600 MHz.

[radar_macgyver]

Duh - I see now that they have included a drop-down next to the 'Impedance' section of the quote page with two options: JLC7628 and JLC2313. These are the names given to the .stackup files they offer for download.

@blueskull could you send me a link to their forum? I can't figure out the right combination of keywords for Google. Thanks!

[radar_macgyver]

Thanks, that was most useful! For reference, JLC produced a test coupon for both their 4-layer stackups, and they measured a section to get 7.6 mil = 0.2mm height. For JLC7628 with a CPWG 12.8 mil = 0.33mm trace, 20 mil (0.508mm) clearance, they measured 50 ohm.  They also posted trace geometry for JLC2313.