OurPCB - affordable multi-layer board manufacturer - my experience

[Koen]

Hello, in which cases do you guys select 2u instead of 1u for Immersion Gold finish ? Thank you. Got 0.4mm QFN's and tiny tiny filters, no BGA, single-reflow, nothing soldered by hand.

[asmi]

Hello, in which cases do you guys select 2u instead of 1u for Immersion Gold finish ? Thank you. Got 0.4mm QFN's and tiny tiny filters, no BGA, single-reflow, nothing soldered by hand.

I think this is mostly needed for gold fingers. My board has 0.4 mm QFN as well, and it soldered OK:


OurPCB had no problems manufacturing solder stops between pins despite them being just over 0.1 mm wide (you can see photos of my board in my blog).

[wraper]

I think this is mostly needed for gold fingers.

ENIG is not suitable for gold fingers, only use on own risk where you don't expect multiple insertions. For gold fingers hard gold plating is used, it's completely different process.
https://www.eurocircuits.com/blog/gold-plating-for-edge-connectors/

[asmi]

BTW, in case anyone is curious - I've assembled the board over weekend, discovered some more issues with schematics and footprints , but they are minor enough such that I was able to fix them right on the board by cutting a couple of traces and soldering in a jumper. I will post a more detailed update to my blog once I have enough time to write it up, also I need to write some HDL to test onboard peripherals, but I already tested the one thing I was worried about the most - which is DDR3L x16 module, and it works like sharm at full 400 MHz (800 MT/s) frequency even using full-strength FPGA drivers. This means that OurPCB made got controlled impedance traces very close to specs, as out-of-spec traces running at 400 MHz without termination would've certainly messed up signal integrity. I also have two 6G diff traces on board (from USB3-FIFO bridge to connector), as well as 4 HDMI diff pairs, so checking if they work will add confidence to specs, but like I said I need to develop HDL components to actually work with them.

[darrell]

I gave them a try on an 8 layer with a few 0.8 mm BGAs and am reasonably pleased with the result. I'm waiting on some parts and expect to assemble next Wednesday. It showed up this morning by Fedex with a hand written label and no shipment notification.

They did some edits on the gerbers which they asked me to approve. Via pads were increased in size and some mask openings were increased. That did remove a few solder mask dams like on U90, but with OSP and lead free solder, it should be fine. In the future, I'll probably specify not to modify solder mask.

I specified ENIG, immersion silver or OSP for the finish (all the flat options). They quoted all three with OSP being $35 cheaper than the others.

I'm probably still doing production in the US, but it was nice to get in another prototype at low cost (about $300 for 10 versus $1800 for the US).

Edit: Forgot to add that they don't stock Isola materials. They asked to subtitute Iteq IT180 for the Isola IS410 I had specified. It's close enough and all the impedances were within 2% on their report.

[asmi]

I gave them a try on an 8 layer with a few 0.8 mm BGAs and am reasonably pleased with the result. I'm waiting on some parts and expect to assemble next Wednesday. It showed up this morning by Fedex with a hand written label and no shipment notification.

I'm probably still doing production in the US, but it was nice to get in another prototype at low cost (about $300 for 10 versus $1800 for the US).

Thanks, this is interesting as I'm thinking of a project which would most likely require 8-layer board. Can you pls show the stackup you used for this design? It looks like "3 cores" to me based on a cross-section - is it so? Your SM offset looks a bit worse than what I had on my boards, but still fairly small if one considers the scale of the proto (U2 looks like DDR3 module, so 0.8 mm pitch part).
Also you use curious footprint to the right of R92 (and a couple at the bottom as well) which seem to have both thru-hole and SMT pads. Is the part really a combination of these, or it's a regular SMT part (VSSOP or TSSOP by the looks of it), and you need open thru-holes for some other reason (like testing, programming, whatever)?
Since I'm a hobbyist, ordering boards in US is absolutely out of question for me due to it being absurdly expensive, so these guys are the enabler as they allow me to make complicated boards without getting a mortgage to pay for production

[darrell]

Thanks, this is interesting as I'm thinking of a project which would most likely require 8-layer board. Can you pls show the stackup you used for this design? It looks like "3 cores" to me based on a cross-section - is it so?

Yes, 3 3.5 mil cores (2x 106 weave glass each). The thickness is chosen so 4 mil inner tracks are 50 ohms and power planes are close to ground planes. The top prepreg gives 5 mils for 50 ohms. I've attached the stack from my fab notes.

In the dense DDR3 region:
top(1): signal
2: ground plane with no traces
3: 1.35 V plane with no traces
4:  ground plane with no traces
5: signal with ground fill
6: signal with ground fill, cross traces on 5 at right angles, thick prepreg helps isolate too.
7: ground plane with no traces
8: signal with ground fill

Other parts of the Zynq have other voltage planes on some of the signal layers.

I probably could have done that in 6 layers, but this way I have no doubts about signal integrity.

Also you use curious footprint to the right of R92 (and a couple at the bottom as well) which seem to have both thru-hole and SMT pads. Is the part really a combination of these, or it's a regular SMT part (VSSOP or TSSOP by the looks of it), and you need open thru-holes for some other reason (like testing, programming, whatever)?

That part is an 8 terminal low ESL capacitor (Murata LLA21 series). The vias are part of the footprint so I don't have to place them for each one. They had openings for another board getting ENIG finish to avoid trapping chemicals and the fab house opened it up further.

[asmi]

Yes, 3 3.5 mil cores (2x 106 weave glass each). The thickness is chosen so 4 mil inner tracks are 50 ohms and power planes are close to ground planes. The top prepreg gives 5 mils for 50 ohms. I've attached the stack from my fab notes.

In the dense DDR3 region:
top(1): signal
2: ground plane with no traces
3: 1.35 V plane with no traces
4:  ground plane with no traces
5: signal with ground fill
6: signal with ground fill, cross traces on 5 at right angles, thick prepreg helps isolate too.
7: ground plane with no traces
8: signal with ground fill

Other parts of the Zynq have other voltage planes on some of the signal layers.

I probably could have done that in 6 layers, but this way I have no doubts about signal integrity.

I only used two signal layers (+ two reference planes of course, all internal) to route out DDR3L x16 (basically two DQ byte groups were on top of each other, and ADDR/CTRL spanned both layers). No SI issues noted even using full-strength FPGA drivers (didn't really need full strength for this board, but I tried it anyway in part to see how much of a margin design has). I was a bit concerned with using outer layers (along with internal) because signal propagation is faster on outer layers than it is on inner. Since I only have a Pro level license for Orcad PCB, it doesn't account for difference of propagation speed when doing trace length matching (I think I will need Allegro level of license to have this feature), as well as different z-length of layers - but that was something I could account to myself by setting offsets to traces based on which layer they go to). This all was probably overkill for DDR3-800, but I kinda prefer to learn doing things the right way from the get-go.

That part is an 8 terminal low ESL capacitor (Murata LLA21 series).

You learn something new every day Thank you again for your responses!

[darrell]

I only used two signal layers (+ two reference planes of course, all internal) to route out DDR3L x16 (basically two DQ byte groups were on top of each other, and ADDR/CTRL spanned both layers). No SI issues noted even using full-strength FPGA drivers (didn't really need full strength for this board, but I tried it anyway in part to see how much of a margin design has). I was a bit concerned with using outer layers (along with internal) because signal propagation is faster on outer layers than it is on inner. Since I only have a Pro level license for Orcad PCB, it doesn't account for difference of propagation speed when doing trace length matching (I think I will need Allegro level of license to have this feature), as well as different z-length of layers - but that was something I could account to myself by setting offsets to traces based on which layer they go to). This all was probably overkill for DDR3-800, but I kinda prefer to learn doing things the right way from the get-go.

Xilinx says not to use the outer layers for DDR with the Zynq. I ignored that rule. I used Kicad and wrote a Python script to generate a trace length matching report which used individual propagation velocities for each layer and accounted for the in package delays. It only took about 20 lines of code if you don't count the lists of nets for each group. The Zynq pinout isn't very good and seems to require more layers.
Of course, that same document with the DDR rules specifies 50 ps matching on I2C and the UART, so some Xilinx rules are best ignored.

My longest Zynq die to DRAM line is 220 ps (160 ps on DQ) and I'm running with no termination as that's significantly less than the rise time. Even the internal terminations on the DQ lines are disabled saving quite a bit of power. The DDR didn't change with the revision and looks fine on the scope. Rise and fall is about 500 ps (scope and probe is 120 ps).

[KE5FX]

I gave them a try on an 8 layer with a few 0.8 mm BGAs and am reasonably pleased with the result. I'm waiting on some parts and expect to assemble next Wednesday. It showed up this morning by Fedex with a hand written label and no shipment notification.

Yow, that mask registration looks pretty terrible.  It's as if your pads are SMD on one side and NSMD on the other...

[Kean]

I gave them a try on an 8 layer with a few 0.8 mm BGAs and am reasonably pleased with the result. I'm waiting on some parts and expect to assemble next Wednesday. It showed up this morning by Fedex with a hand written label and no shipment notification.

Yow, that mask registration looks pretty terrible.  It's as if your pads are SMD on one side and NSMD on the other...

Really?  It looks to be fine to me.  It doesn't cover the pads at all.
Solder mask regsitration is typically +/- 2mil (0.05mm) which is why soldermask is normally specified as 2mil larger than the pad.

[asmi]

Really?  It looks to be fine to me.  It doesn't cover the pads at all.
Solder mask regsitration is typically +/- 2mil (0.05mm) which is why soldermask is normally specified as 2mil larger than the pad.

Yea I don't see any issues as well. Microphotos can often be very deceiving because it's not easy to "feel" the scale. Even when I look through stereo microscope with my own eyes, I sometimes have to put some kind of "known" object into the field of view to really "feel" the scale. If you look at your very own finger under x20 stereo microscope, it's not easy to figure out that it indeed is a finger, because it looks more like a mountain

[wraper]

I had much better alignment on PCBs with 0.5mm pin pitch ICs and ENIG, and about like this on cheaper PCBs with a bit larger parts and lead free HASL. In any case this is order of magnitude better alignment compared to what you'll get from pcbway.

[NorthGuy]

I think it looks bad because the solder mask opening on these capacitor holes is about 2mil smaller than the copper ring (1mil from each side). The solder mask is shifted South-West 1.5 - 2mil, which cause the North-Eastern side to be completely covered, which looks weird.

On the pads, where solder mask opening looks about 4mil wider than the pad (2mil from each side), it looks very good. You can see a gap between the pad and solder mask on all sides. Which means that the solder mask misplacement is less than 2 mil.

Darrell has said that they extended solder mask openings. What was the gap between pads and solder mask in the original Gerbers and how much they extended it? I wonder why they didn't extend the solder mask openings on the capacitor holes?

[darrell]

I think it looks bad because the solder mask opening on these capacitor holes is about 2mil smaller than the copper ring (1mil from each side). The solder mask is shifted South-West 1.5 - 2mil, which cause the North-Eastern side to be completely covered, which looks weird.

On the pads, where solder mask opening looks about 4mil wider than the pad (2mil from each side), it looks very good. You can see a gap between the pad and solder mask on all sides. Which means that the solder mask misplacement is less than 2 mil.

Darrell has said that they extended solder mask openings. What was the gap between pads and solder mask in the original Gerbers and how much they extended it? I wonder why they didn't extend the solder mask openings on the capacitor holes?

The original gerbers had 50 um (2 mil) each side mask to pad clearance. They didn't change that, just increased the opening where there is was an exposed via. The mask is shifted almost 2 mils. Much more and they would have needed to redo it, but it will be fine. I've seen worse from far more expensive board houses. The drills are shifted a few mils in the opposite direction.

[asmi]

The original gerbers had 50 um (2 mil) each side mask to pad clearance. They didn't change that, just increased the opening where there is was an exposed via. The mask is shifted almost 2 mils. Much more and they would have needed to redo it, but it will be fine. I've seen worse from far more expensive board houses. The drills are shifted a few mils in the opposite direction.

Speaking of drills, what size did you use for breakout area? I used 0.2 mm drill and 0.45 mm pad vias, but I wonder if someone tried using smaller ones. It would be cool if it would be possible to somehow fit two traces between breakout vias for 0.8 mm pitch part, but I suspect that's going to require via-in-a-pad or microvias. Although dynamic unused pads suppression (removing unconnected pads for vias from internal layers where there is no connection to them on that layer) could help with that as this way you will only be limited by drill-to-copper constraint.

[darrell]

Yea I don't see any issues as well. Microphotos can often be very deceiving because it's not easy to "feel" the scale. Even when I look through stereo microscope with my own eyes, I sometimes have to put some kind of "known" object into the field of view to really "feel" the scale. If you look at your very own finger under x20 stereo microscope, it's not easy to figure out that it indeed is a finger, because it looks more like a mountain

Here's the previous revision, made in USA for about $1600. As you can see, it's a bit worse. Those soldered just fine. Both boards look fine to the naked eye or even with a loupe. My photo setup is about 6.4 um per pixel (Canon SLR with 100 mm  f/2.8 macro).

[darrell]

Speaking of drills, what size did you use for breakout area? I used 0.2 mm drill and 0.45 mm pad vias, but I wonder if someone tried using smaller ones.

0.46 mm pad, 0.2 mm drill. I don't think OurPCB is had good enough drill registration to get two traces between vias on 0.8 mm. Xilinx does it on some eval boards, so it can be done.

[asmi]

0.46 mm pad, 0.2 mm drill. I don't think OurPCB is had good enough drill registration to get two traces between vias on 0.8 mm. Xilinx does it on some eval boards, so it can be done.

If you remove unused pads, you will have 0.6 mm drill-to-drill, but even if you reduce it to 0.5 mm (to allow ±0.05 mm drill positioning tolerance) that still is enough to put two 0.1 mm traces and three 0.1 mm spacings.
I will try this on my next design that's going to have 32 bits wide memory bus so chances are I will need any routing space I can get.

[darrell]

0.46 mm pad, 0.2 mm drill. I don't think OurPCB is had good enough drill registration to get two traces between vias on 0.8 mm. Xilinx does it on some eval boards, so it can be done.

If you remove unused pads, you will have 0.6 mm drill-to-drill, but even if you reduce it to 0.5 mm (to allow ±0.05 mm drill positioning tolerance) that still is enough to put two 0.1 mm traces and three 0.1 mm spacings.
I will try this on my next design that's going to have 32 bits wide memory bus so chances are I will need any routing space I can get.

The problem is 0.2 mm is the finished via size. Most shops drill that with an 0.25 mm bit to allow for plating. I think OurPCB likely used an 0.3 mm on mine as the holes are bigger than the last revision (confirmed from cross section photo measurements). They were off by as much as 0.08 mm (measured) on drill positioning with my board. I think you would have to go with 0.075 mm traces and spaces to do it as Xilinx did and you might still need a better boardhouse. I'd probably go for more layers instead. I wish these parts were 1 mm pitch for that purpose.

[asmi]

The problem is 0.2 mm is the finished via size. Most shops drill that with an 0.25 mm bit to allow for plating. I think OurPCB likely used an 0.3 mm on mine as the holes are bigger than the last revision (confirmed from cross section photo measurements). They were off by as much as 0.08 mm (measured) on drill positioning with my board. I think you would have to go with 0.075 mm traces and spaces to do it as Xilinx did and you might still need a better boardhouse. I'd probably go for more layers instead. I wish these parts were 1 mm pitch for that purpose.

I think I'm gonna give it a try anyways. Will see what happens Would be interesting how they handle that. Technically they are able to do 3 mil traces/spacing, so if above plan won't work, I will just make traces narrower.

[asmi]

I've finally tested USB 3.0 communication via FT601. In single channel mode it achieved 323 MBytes/s (~2.5 GBit/s) of actual data bandwidth, which matches what FTDI says it should be, so I conclude that 5GBit transmission lines on the board work as they should, and it's impedance is right on the mark (multi-GBit lines are famous for very strict tolerances).
Also I gotta say that I really like this bridge chip - so simple to work with yet so powerful. If only it wouldn't cost as much as it is (and "consume" so many IO pins) I'd stick it to all my designs!

[wraper]

I've finally tested USB 3.0 communication via FT601. In single channel mode it achieved 323 MBytes/s (~2.5 GBit/s) of actual data bandwidth, which matches what FTDI says it should be, so I conclude that 5GBit transmission lines on the board work as they should, and it's impedance is right on the mark (multi-GBit lines are famous for very strict tolerances).

USB 3.0 works even on 2 layer board without remotely adequate impedance and trace length matching. With one issue though, wireless mouses, keyboards and wifi perform erratically or just die nearby such thing when you, say, transfer files to memory stick.

[darrell]

Really?  It looks to be fine to me.  It doesn't cover the pads at all.
Solder mask regsitration is typically +/- 2mil (0.05mm) which is why soldermask is normally specified as 2mil larger than the pad.

Yea I don't see any issues as well. Microphotos can often be very deceiving because it's not easy to "feel" the scale. Even when I look through stereo microscope with my own eyes, I sometimes have to put some kind of "known" object into the field of view to really "feel" the scale. If you look at your very own finger under x20 stereo microscope, it's not easy to figure out that it indeed is a finger, because it looks more like a mountain

In case anyone is curious, here's that same area on the same board populated. The solder on the ugly QFN and 8 terminal capacitor turned out fine. Everything works and only one resistor value change was required in bringup.

[asmi]

In case anyone is curious, here's that same area on the same board populated. The solder on the ugly QFN and 8 terminal capacitor turned out fine. Everything works and only one resistor value change was required in bringup.

Sounds like you just saved yourself enough money for 5 more iterations
That QFN looks familiar... TLV62130? I use it on my board as pre-regulator for TPS65400 main PMIC.