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prepare board design for component shortage - hand assembly - single ic stencil

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These days it's common that I get SMD assembled boards that still lack a few ic's. JLCPCB etc. Even before chipageddon, there were a few chips that I had to source from elsewhere anyway, and then 'hand solder' one way or the other with my IR rework station.
Typically the missing chips are those with the highest pin counts, so the most challenging to hand solder. Mostly the microcontrollers and FPGAs that one day (year?) will be available again. So I end up recycling QFN, QFP, BGA, LGA ic's from older scrap boards so that at least my new prototype boards can be tested and debugged. Not having a mini stencil for just those single ic's so that I can get proper solder paste deposited manually but consistently is where I struggle. Alignment of the stencil, accurately, on a board that is mostly populated already, is a challenge for me. So I'm considering board designs with two (three? four?) 'mini stencil alignment' holes nearby the difficult to get ic footprints. Nearby or under it. Just so that I can cut out from a full board stencil that also got these alignment holes.

Now the question: are there any recommended / standard ways of doing this? Kicad libraries for such ic footprints? Can I buy single ic mini stencils from somewhere and if yes, where do they have alignment holes? What size are the holes? I did find some large BGA stencils - but even those lack alignment holes.     

I've never used one but you can buy rework stencils like these https://www.intertronics.co.uk/product/flextac-bga-rework-stencils/ or https://www.solder.net/rework-stencils/ the stencil mate one is particularly interesting and I have mimicked that "bumping" technique using an old stencil on a QFN device before with good results. With sufficient patience and skill most QFN & QFP packages can be managed with flux, smart wire and a soldering iron or hot air. In theory you don't need to paste a BGA, if the BGA is in decent condition, well stored & reballed if needed, flux and heat is all you need.

If you can unsolder QFNs then you certainly have a heat gun. You can use it to solder them back. You don't have to use a paste. Just put the solder on the pads with a big soldering iron, clean, add flux, place the component and heat from the top. Or you can put it in the oven if you need to solder several components at a time.

BGA should be re-balled. But you can get away without reballing. Just put solder on the footprint and then put solder onto the bottom of the BGA. Then clean, flux and heat. This may work just as well as reballing.

For prototyping you can use leaded flux which has lower melting point and is easier on the components. You also don't need to worry about long term. So, less-than-perfect methods are quite acceptable.

As long as you have components to solder ...

I've taken to making my own stencils out of mylar OHP film for these  sort of little jobs.

(Click to enlarge)

I cut them on Silhouette Portrait vinyl cutter normally sold for art and craft uses. I picked mine up on eBay for about £50 specifically to cut stencils with, but it has also earned its keep cutting vinyl for signs, T-shirts and even front panel markings.

I shall not offer instructions for doing this. If you're interested you can find the gory details with google. I will note that I found the code at https://github.com/pmonta/gerber2graphtec.git highly useful.

[attach=3]Thank you all for suggestions and links today. Back to my original question: what is a good practice for adding local-mini-stencil-alignment-holes in a KiCad (5.1) project.
This is what the board design looks like now, but with that it's quite hard to deposit solder paste when JLCPCB did not place the 48+1 pin, the 100 pin QFP ics for me. So I get a board with nearly all the SMD components already assembled, but now it's my job to get the 49 QFN and that 100 pin IC8 also soldered to this board.

My thinking now is that next time around, I can make my life easier if I also order the stencil, and have in the stencil some (2 or more) alignment holes. Those holes could well be open (unpotted!) vias that I have around the ics anyhow. From the stencil I will cut out with a pair of scissors the ~1 square inch area that surrounds just the ic footprint, plus the alignment holes.

So what I maybe need is a special type of via. One that has an ID hole size or say 0.5 or 1.0 mm. And that is defined on the F.Paste as a same size hole. Is there such a via footprint / symbol defined anywhere in KiCad libraries or do I need to make it from scratch? Or are there footprints for such ic's that have some alignment holes, say 4, one at at each corner?

I've seen https://www.pcbway.com/blog/PCB_Design_Tutorial/A_very_easy_way_to_accurately_align_the_stencil_with_the_PCB_1.html which does what I want for a full board. But now I want it just for a local stencil that does 1 ic only.


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