1. Altium at least supports rules for edge clearance, and most other mechanical features, or electrical features on the same layer.
2. Acute angle is also on there. AFAIK, acid trapping isn't a problem these days; personally, I just avoid it because it's ugly. Smooth your routes, it's called artwork for a reason?
3. Assembly issue. Can be accommodated, or mitigated; generally not recommended. Fab alternative: filled and capped vias ($$).
7. I like to keep the number of drill items short. Given the tolerance (or house tolerance if you don't specify!!), they'll just bin everything into the nearest sizes they have; it's your problem whether that still fits or not. Best practice, specify tolerance and check it against the real components. Follow proper mechanical drafting practice!
??. Thermal relief is not one that Altium for instance has, and even some enterprise DFM tools (e.g. Valor) don't always get right. Best to keep a watch for this while you're working -- repour polygons from time to time and check if they're drawing more spokes to some pads than there are traces on the other pads.
Only affects chips (R, C, etc.), particularly small ones (0603-). Larger ones tend not to tombstone, and more pads, tend not to twist or tombstone. Tombstone, head-on-pillow and such failures are the main issue, a production yield problem.
Don't go nuts with thermal relief. You don't need teeny spokes on every damn pad. Conversely, don't go nuts against it. You don't need solid pours all around the pad, basically anywhere. Go ahead, calculate the thermal resistance of average sized spokes, I'll wait! -- We should be so fortunate, to work in a field where so much (in principle,
everything) can be calculated directly, or at least modeled! -- you'll find that the effect on thermal resistance isn't too much, a few °C here or there, while the improvement in soldering is substantial (both reflow and hand soldering). Basically, soldering delivers much higher heat flux, and takes a smaller temp drop (most of the board is already near soldering temp, in reflow), than is the case for heat dissipated by passive convection.
I normally scale spokes, so that the clearance (pad to pour) is whatever, 10 mils say, and the spokes are 4 x 10 mil width. Thinner for small SMT pads (under say 20 mil width), wider for larger pads (say 20 for >70 mil pads, 30 for >150, etc.). This keeps everything from 0402 chips to D2PAK thermal pads readily solderable.
And you can always double down, in those few cases where you need more.
Example: a D2PAK can dissipate almost 10W on a conventional 4 layer board, maybe even 2 layer (2oz copper). To pull it off, you need solid pours -- no spokes -- on both sides, and lots of vias to bring the heat between them.
Moreover, the vias can be filled with solder, reducing their Rth almost in half. (Yes, solder is a poor enough conductor that a via fully loaded with the stuff, barely performs better than the hole lined with just a thin foil of copper! BTW, lead-free is better in this respect; in general, alloys conduct worse than their constituents, and SAC305 has much less alloying than Sn60.) Bonus points for via-in-pad, but only if the assembly is reasonable -- for example, maybe you can't ensure adequate reflow of a D2PAK with tons of via-in-pad on its tab, but maybe they get filled on a subsequent wave soldering step. (Or if you're doing it by hand, just flood the bastard, eh?)
Finally, now that you've got the heat spread out on both sides of the board, clamp it between two heat sinks, with thermal pads. Thermal pads aren't great either (typically 1 W/(m.K); though 3, 6, even 10 and higher are available these days!), but you're using a wide area of them so it works out.
FR-4 itself is mediocre on conductivity, in-plane, and downright dismal thru-plane. The lateral thermal conductivity is about, what was it, doubled or so? by pouring copper on the outside, and obviously, that much more still with inner layers. Thru conductivity is dominated by vias; the only case where FR-4 is acceptable is when it's already very thin, like traces and pads to inner planes. (Indeed, this is enough conductivity that trace ampacity is increased markedly -- double or so -- when routed over inner planes!)
Tim